Self-refresh semiconductor memory device responsive to a refresh

Details Self-refresh semiconductor memory device responsive to a refresh Self-refresh semiconductor memory device responsive to a refresh

1989-11-27

1991-01-01

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365210, 365149, 365194, G11C 700

Patent

active

049823698

ABSTRACT:
A semiconductor memory device carrying out a self-refresh operation in response to a refresh request signal. The device includes a memory cell array formed on a chip; a plurality of pseudo memory cells distributed and arranged on the chip, each having the same constitution as the memory cells in the memory cell array; a first circuit for monitoring the capacitor voltage in the pseudo memory cells; and a second circuit for generating the refresh request signal and charging each capacitor in the pseudo memory cells. When the potential of at least one of the capacitors in the pseudo cells falls below a predetermined level, the refresh request signal is generated, thereby enabling the device to lengthen a refresh interval as desired and to decrease power dissipation, while facilitating work requiring any adjustment.

REFERENCES:
patent: 4360903 (1982-11-01), Plachno et al.
patent: 4677590 (1987-06-01), Arayawa
patent: 4682306 (1987-07-01), Sakurai et al.
patent: 4734890 (1988-03-01), Miyatake et al.
patent: 4794571 (1988-12-01), Uchida
patent: 4809233 (1989-02-01), Takemae
System Design/Integrated Circuits, Computer Design, vol. 22, Mar. 1983, No. 3, "The Chip That Refreshes Itself", by J. J. Fallin et al.
Sawada et al., VLSI Symposium 1986, p. 85, Semiconductor Device Engineering Laboratory, "Self-Aligned Refresh Scheme".

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