Self-refresh period adjustment circuit for semiconductor memory

Static information storage and retrieval – Read/write circuit – Data refresh

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365211, 36518907, G11C 11402

Patent

active

056803591

ABSTRACT:
A self-refresh period adjustment circuit for a semiconductor memory device. The self-refresh period adjustment circuit comprises a ring oscillator for generating a pulse signal with a fixed period for a self-refresh operation of the semiconductor memory device, a leakage current detector for detecting the amount of leakage current produced as charges stored in memory cells in the semiconductor memory device are discharged, and at least two temperature detectors for detecting a temperature variation of the semiconductor memory device, each of the at least two temperature detectors including a voltage divider and a comparator. The voltage divider divides a supply voltage and supplies the divided result as a reference signal to the comparator. The comparator compares an output signal from the leakage current detector with the reference signal from the voltage divider. The self-refresh period adjustment circuit further comprises at least two frequency dividers, each of the at least two frequency dividers dividing a frequency of an output signal from the ring oscillator at a desired ratio in response to an output signal from a corresponding one of the at least two temperature detectors to adjust a self-refresh period of the semiconductor memory device.

REFERENCES:
patent: 4716551 (1987-12-01), Inagaki
patent: 5278796 (1994-01-01), Tilinghast et al.
patent: 5495452 (1996-02-01), Cha
patent: 5532968 (1996-07-01), Lee
patent: 5596533 (1997-01-01), Park

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