Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2011-08-16
2011-08-16
Phan, Trong (Department: 2827)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S189070, C365S189120, C365S230030, C365S240000
Reexamination Certificate
active
08000163
ABSTRACT:
A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.
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“Dual-Period Self-Refresh Scheme for Low-Power DRAM's with On-Chip PROM Mode Mode Register” by Youji Idel et al.,IEEE Journal of Solid-State Circuits, vol. 33, No. 2, Feb. 1998, pp. 253-259.
Ahn Jin-Hong
Chu Shin-Ho
Jeong Bong-Hwa
Kim Saeng-Hwan
Blakely & Sokoloff, Taylor & Zafman
Hynix / Semiconductor Inc.
Phan Trong
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