Self-refresh controlling apparatus

Details Self-refresh controlling apparatus Self-refresh controlling apparatus

2000-12-26

2001-12-25

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189050

Reexamination Certificate

active

06333886

ABSTRACT:

BACKGROUND
1. Field of the Invention
The claimed inventions relate, at least generally, to a self-refresh controlling apparatus. More specifically, some of the claimed inventions feature a self refresh controlling apparatus capable of stabilizing circuit operation.
2. General Background and Related Art
Generally, self-refresh denotes a refresh operation performed internally with a predetermined period to maintain data stored in a memory cell during a waiting state in a semiconductor memory as a DRAM (Dynamic Random Access Memory).
A problem occurs due to the difficulty of adjusting the timing between the signal synchronized with the external clock signal and the signal not synchronized with the external clock signal. Furthermore, when a variety of frequencies should be adjusted, proper delays are required and the problem becomes more serious.
FIG. 1
(Prior Art) is a block diagram of a conventional self-refresh controlling apparatus. The apparatus includes a clock enable signal buffer
10
for buffering an externally provided clock enable signal cke and generating a self-refresh exit control signal s_ref_exit. A self-refresh logic
20
controls activation of a clock buffer enable control signal buf-en by performing the self-refresh operation depending on the state of the self-refresh exit control signal s_ref_exit from the clock enable signal buffer
10
. A clock buffer
30
receives the clock buffer enable control signal buf-en for comparing the potential of an external input clock signal ext_clk with a reference to generate an internal clock signal int_clk. A command and address latch
40
latches a command and an address buffered with the internal clock signal int_clk in synchronization with the external clock signal ext_clk.
FIG. 2
(Prior Art) is a timing diagram explaining the operation of the self refresh controlling apparatus shown in
FIG. 1
(Prior Art). The clock buffer enable control signal buf_en generated under control of the clock enable signal cke as shown in (d) is a signal generated that is not synchronized with the external clock signal ext_clk.
Therefore, when the external clock signal ext_clk is logic high during activation of the clock buffer
30
, the internal clock signal int_clk is generated latter as shown in (c).
The self refresh controlling apparatus latches the output signal of a command and address buffer (not shown) in synchronization with the external clock signal ext_clk at the command and address latch
40
by using the internal clock signal int_clk. The output signal of the command and address buffer is adjusted so that it is applied from an external source as its set-up time and hold time match.
Subsequently, when the internal clock signal int_clk is activated latter as described above, the set-up time and the hold time of the output signal from the command and address buffer does not match, which leads error in operation that adversely affects circuit stability.
SUMMARY
The claimed inventions feature, at least in part, a self refresh controlling apparatus capable of stabilizing circuit operation. This stabilization is achieved by preventing failure after self refresh by matching the set-up time and the hold time of the clock buffer output signal by adjusting timing between the signal synchronized with the external clock signal and the signal not synchronized with the external clock signal. Accordingly, the self-refresh controlling apparatus of the present invention is useful for use with any semiconductor memory apparatus performing self-refresh.
An exemplary embodiment of the claimed inventions provides a self refresh controlling apparatus including a first buffering unit for buffering a clock enable signal received from an external source to generate a self refresh completion control signal. A self refresh logic controls activation of a clock buffer enable control signal by performing self refresh operation depending on the state of the self refresh completion control signal from the first buffering unit. A second buffering unit receives the clock buffer enable control signal for comparing a potential of an external clock signal with a reference potential to generate an internal clock signal. A delay unit delays the clock buffer enable control signal by a predetermined time. An internal clock signal activation controlling unit controls activation of the internal clock signal by logically combining the internal clock signal with a control signal generated under control of the delayed clock buffer enable control signal from the delaying unit and the internal clock signal. A latching unit latches, in synchronization with the external clock signal, a command and an address buffered by the internal clock signal of which timing is adjusted at the internal clock signal activation controlling unit.


REFERENCES:
patent: 6195303 (2001-02-01), Zheng

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