Self refresh control circuit for memory cell array

Details Self refresh control circuit for memory cell array Self refresh control circuit for memory cell array

1995-02-22

1996-07-02

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Data refresh

36518907, 36518909, 365193, 365236, G11C 700

Patent

active

055329683

ABSTRACT:
A self refresh control circuit for a memory cell array including a plurality of address buffers for inputting addresses of the memory cell array and a plurality of decoders for decoding the addresses from the address buffers. The self refresh control circuit further includes a self refresh mode control circuit for controlling a self refresh operation of the memory cell array in response to a row address strobe signal and a column address strobe signal, a reference voltage generator for generating a plurality of reference voltages, each of the reference voltages being nearly constant in level regardless of a temperature variation in a chip, and a temperature tracing circuit for generating a voltage variable with the temperature variation in the chip, comparing the generated variable voltage with the reference voltages from the reference voltage generator, respectively, selecting a desired one of a plurality of self refresh periods from the self refresh mode control circuit in accordance with the compared results and outputting the selected self refresh period to the self refresh mode control circuit.

REFERENCES:
patent: 4982369 (1991-01-01), Tatematsu
patent: 4984210 (1991-01-01), Kumanoya et al.
patent: 5027327 (1991-06-01), Kobayashi et al.
patent: 5375093 (1994-12-01), Hirano
patent: 5406522 (1995-04-01), Hirano
patent: 5479372 (1995-12-01), Sato et al.

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