Self refresh circuitry for dynamic memory

Details Self refresh circuitry for dynamic memory Self refresh circuitry for dynamic memory

1984-08-31

1987-03-24

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Data refresh

307475, G11C 700

Patent

active

046530304

ABSTRACT:
A semiconductor dynamic read/write memory of the multiplexed-address type employs an on-chip refresh counter which is activated by CAS-before-RAS sequence. This counter is made up of stages almost identical to the row address buffers so the same clocks can be used. Either the address input buffers or the refresh counter stages are gated into second-stage row address buffers, and carry feedback from these second stage buffers to the counter stages is used to increment the counter. The access time of the memory for normal read or write is not degraded by the refresh circuitry.

REFERENCES:
patent: 4110639 (1978-08-01), Redwine
patent: 4239993 (1980-12-01), McAlexander III et al.
patent: 4342103 (1982-07-01), Higuchi et al.

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