Self-refresh based power saving circuit and method

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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C365S230060

Reexamination Certificate

active

07986580

ABSTRACT:
A circuit includes a memory interface control circuit and a self-refresh adjustable impedance driver circuit having at least one adjustable impedance circuit. The memory interface control circuit selectively provides an impedance control signal based on memory self-refresh information. The self-refresh adjustable impedance driver circuit adjusts an impedance value of the adjustable impedance circuit in response to the impedance control signal. In addition, the self-refresh adjustable impedance driver circuit provides a memory interface signal based on the memory self-refresh information.

REFERENCES:
patent: 6832177 (2004-12-01), Khandekar et al.
patent: 7019553 (2006-03-01), Blodgett et al.
patent: 7459930 (2008-12-01), Mei
patent: 7633310 (2009-12-01), Fukushi
patent: 2008/0168262 (2008-07-01), Bellows et al.

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