Static information storage and retrieval – Read/write circuit – Erase
Patent
1993-08-17
1995-03-21
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Erase
365900, G11C 1300
Patent
active
054002869
ABSTRACT:
Word line stress is used to narrow the distribution of threshold voltages after an erase of an array of memory cells. One embodiment of the invention provides a method for erasing an array including a standard erase technique followed by extra erase pulses to create a margin between threshold voltages of the cells and the erase verify level, then applying word line stress to narrow the distribution of threshold voltages. Another embodiment in addition includes verifying that all of the memory cells are still erased after applying word line stress and if any of the memory cells were over-stressed and are not erased, repeating the method but using less word line stress. The erase methods according to embodiments of the present invention can be implemented by an external CPU which executes an erase program or by circuitry embedded in an EEPROM.
REFERENCES:
Yamada, "A Self-Convergence Erasing Scheme for Simple Stacked Gate Flash EEPROM," IEDM 1991, pp. 307-308.
Endoh, "New Write/Erase Operation Technology for Flash EEPROM Cells to Improve the Read Disturb Characteristics," IEDM 1992, pp. 603-606.
Oyama, "A Novel Erasing Technology for 3.3V Flash Memory . . . ," IEDM 1992, pp. 607-610.
Chu Sam S. D.
Ho Calvin V.
Catalyst Semiconductor Corp.
Fears Terrell W.
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