Self-quenching memory cell

Details Self-quenching memory cell Self-quenching memory cell

1977-12-05

1978-11-28

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

307291, G11C 1140

Patent

active

041278992

ABSTRACT:
A memory array comprising a matrix of cells each of which includes a pair of bipolar transistor inverters. The collector loads of the inverters are commonly connected to a first constant voltage buss. The emitters of the transistors are commonly connected through a second resistor to a second constant voltage buss. Separate writing and reading circuits are provided for each cell in the array so that array cells can be written into and read from simultaneously.

REFERENCES:
patent: 3675218 (1972-07-01), Sechler
patent: 3732440 (1973-05-01), Platt et al.
patent: 3973246 (1976-08-01), Millhollan et al.
Wiedmann, Random Access Memory Cell, IBM Technical Disclosure Bulletin, vol. 14, No. 6, 11/71, pp. 1721-1722.
Berding, Simultaneous Read-Write Monolithic Storage Cell, IBM Technical Disclosure Bulletin, vol. 13, No. 3, 8/70, p. 620.

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