Self programmed built in self test

Details Self programmed built in self test Self programmed built in self test

1997-07-02

2000-08-22

Bragdon, Reginald G.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714733, 711105, G01R 3128, G06F 1326, G06F 1127

Patent

active

06108798&

ABSTRACT:
A memory (e.g. , Dynamic Random Access Memory (DRAM)) with self-programmable Built In Self Test (BIST). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BIST Engine, a Command Register and a Self-Program Circuit. During self test, the BIST engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.

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