Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-01-11
2005-01-11
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S057000, C326S027000
Reexamination Certificate
active
06842038
ABSTRACT:
The present invention provides apparatus and methods to eliminate a required “dead cycle” or “living cycle” during transfer of control from a first source terminated driver to a second source terminated driver on a bidirectional signaling conductor. On a last bus cycle on which the first driver drives the signaling conductor, the first driver stops driving and goes into a high impedance state respondent to detection that the first driver current has become lower than a predetermined current or that a voltage at the output of the first driver has become within a predetermined voltage difference of a target voltage. The second driver, knowing that the first driver will be switched to a high impedance state, can assume control of the signaling wire and drive a signal on the signaling conductor shortly after receipt of the signal from the first driver.
REFERENCES:
patent: 6020757 (2000-02-01), Jenkins, IV
patent: 6329835 (2001-12-01), Chen
patent: 6690191 (2004-02-01), Wu et al.
Bartley Gerald Keith
Ericson Richard Boyd
Germann Philip Raymond
Cho James H.
Williams Robert R.
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