Self-nesting interrupts

Electrical computers and digital data processing systems: input/ – Interrupt processing

Reexamination Certificate

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Details

C710S264000, C710S266000, C710S261000

Reexamination Certificate

active

07043582

ABSTRACT:
A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.

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Adam Osborne, “Unterbrechungssteuerung”,Einführung in die Mikrocomputer-Technik, pp. 5-76 to 5-106 & 7-60 to 7-63 (1982).

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