Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-03-03
2002-09-03
Rinehart, Mark H. (Department: 2152)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S108000, C709S213000, C709S216000, C711S152000, C711S163000
Reexamination Certificate
active
06446149
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to synchronization between multiple busmasters in a computer system, and more particularly to a self-modifying synchronization memory address space and protocol for communication between multiple busmasters.
2. Description of the Related Art
For computer systems including heterogeneous busmasters and loosely coupled busses, such as distributed computer systems and certain multiprocessor computer systems, shared memory synchronization between multiple busmasters is a primary concern. While homogenous busmasters are generally able to communicate directly with one another, synchronization between heterogenous busmasters and between certain homogenous busmasters, which are unable to communicate directly with one another, has typically required host processor intervention. Host processors have allowed for exclusive accesses by heterogenous busmasters to shared memory by issuing atomic transactions. An atomic transaction is a transaction including operations which are performed without interference from other processes. Atomic transactions have typically included assertion of a bus locking signal. An atomic transaction for achieving an exclusive access for a busmaster has included at least two operations, a read operation and a write or set operation. A semaphore memory variable is a flag object for coordinating exclusive access to a critical region of a shared memory. During a read operation, a semaphore memory variable is read, and during a write or set operation, a value is written to the semaphore memory variable. Implementing atomic transactions has required special processor instructions for performing a sequence of real and write operations. Examples of special processor instructions include ‘swap’ instructions, memory exchange instructions, ‘test & set’ instructions, and ‘read-modify-write’ instructions. The most prevalent special processor instruction has been the ‘read-modify-write’ instruction. Each special processor instruction, like the ‘read-modify-write’ instruction, essentially performs a read-modify-write cycle. Also, in implementing atomic transactions, it has been necessary to launch an atomic transaction on a bus having a bus protocol supporting the particular special processor instruction.
An algorithm including a special processor instruction for performing a read-modify-write cycle, such as the ACQUIRE_SPINLOCK routine provided in Windows NT®, is used to synchronize access to a shared memory between multiple busmasters. The routine is initiated by a busmaster seeking to determine if a semaphore memory variable may be claimed. The special processor instruction commonly used in the ACQUIRE_SPINLOCK routine to perform a read-modify-write cycle is the Exchange instruction. The Exchange operation is an intrusive operation which includes an assertion of a bus locking signal by a processor.
A bus locking signal such as Intel's LOCK# signal on the X86 processors is typically used in connection with an atomic transaction to permit a busmaster to attempt to claim a semaphore memory variable. When a bus locking signal is asserted, the associated bus is locked, preventing other busmasters from acquiring ownership of the bus and, thus, access to the semaphore memory variable. The locked cycle of the busmaster terminates when the bus locking signal is deasserted. A bus locking signal undesirably consumes or narrows bandwidth of the associated bus. A bus locking signal also has the drawback of being specific for a particular bus locking architecture. For example, a PCI master is presently unable to initiate a LOCK# signal onto a host bus. A further disadvantage is that assertion of a bus locking signal forces posted writes within a host processor to be flushed to main memory.
SUMMARY OF THE INVENTION
Briefly, the system and method according to the present invention provides a synchronization memory address space and synchronization memory protocol for communication between multiple busmasters in a computer system. The self-modifying synchronization memory address space is preferably located in a memory controller embedded in a peripheral device such as a bridge that provides central, high speed access by a busmaster to the memory controller without accessing a host bus. The address space includes a set of semaphore memory cells mapped to shared critical resources in the computer system. Each region of the self-modifying synchronization address space corresponding to a particular shared critical resource serves as a synchronization memory channel.
The semaphore memory cell allows for exclusive access by a busmaster to a shared critical resource by switching itself from an idle state to a busy state responsive to a first read operation by a busmaster. In the busy state of the semaphore memory cell, a busy state is communicated to other busmasters which attempt to read the semaphore memory cell. Ownership of the semaphore memory cell is thus achieved using a single operation by a busmaster.
Further, the semaphore memory cell responsive to a write operation by a busmaster owning the semaphore memory cell switches itself from a busy state back to an idle state. A semaphore memory cell having an idle state is available to be claimed by a busmaster. The write to the semaphore memory cell by a busmaster may be broadcast to other busmasters. Sideband signals are defined to detect when the bridges associated with the target busmasters are ready to receive the broadcast write. If the target busmaster to receive the broadcast write is associated with a different host bridge than the busmaster initiating the write to the semaphore memory cell, the host bridge associated with the initiating busmaster may reflect the write to the host bridge associated with the target busmaster. A broadcast write may also serve to invalidate a cache line of the target busmaster corresponding to the semaphore memory cell to which a value has been written.
Each bridge in the computer system preferably includes a synchronization bridge configuration register. A synchronization bridge configuration register allows a bridge to determine whether a target address provided by a busmaster is mapped to the self-modifying synchronization memory address space, whether the synchronization memory channel local to the bridge is enabled, and whether a bridge is reflector enabled so as to allow the bridge to reflect a write to another bridge. The synchronization bridge also may indicate the location of the synchronization memory channel local to the bridge.
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Bonola Thomas J.
Moriarty Michael P.
Shaver Charles N.
Walrath Craig A.
Akin Gump Strauss Hauer & Feld & LLP
Compaq Information Technologies Group L.P.
Rinehart Mark H.
Willett Stephan
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