Self-initializing chipset

Details Self-initializing chipset Self-initializing chipset

1999-12-10

2003-10-21

Heckler, Thomas M. (Department: 2185)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

Reexamination Certificate

active

06636962

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computers having chipsets, and more particularly, to a method and apparatus for self-initializing a chipset.
2. Description of the Related Art
FIG. 1
is block diagram of a prior art computer system
10
having a processor
12
, a main memory device
14
, a nonvolatile memory device
16
, and one or more chipsets
18
. All of the components in
FIG. 1
are interconnected through a main bus
20
(also referred to as the “processor bus”).
The main memory device stores program code for the operating system and for high-level applications. The nonvolatile memory device stores system firmware program code which the processor executes when performing low-level hardware-specific operations. The system firmware program code includes a boot portion, which is executed when the system is reset, and a run-time services portion, which is executed utilized after system has reached a normal operating state. Each one of the chipsets is generally associated with a major functional block of the system. For example, in a system based on an Intel® Pentium® II processor, one of the chipsets includes the “north bridge” and “south bridge” chips, which interface the main bus to other buses in the system. Some chipsets might only have a single chip, for example, a video display driver chip, and some systems might only have a single chipset.
When the system is reset, it goes through a boot process wherein the processor performs all of the tasks required to bring the system to the normal operating state. A prior art boot process
22
is illustrated in FIG.
2
. The boot process begins when the system is reset at
24
. At
26
through
30
, the processor executes the boot portion of the system firmware code which causes the processor to sequentially initialize the chipsets by loading configuration data into configuration registers in the chipsets through the main bus
20
. The system firmware boot code then performs other boot tasks, for example, initializing devices at
32
through
36
. Control of the processor is then passed to a boot portion of the operating system code at
38
.
FIG. 3
is a block diagram of a prior art chipset. The chipset
40
includes a set of configuration registers
42
. Although most practical chipsets are likely to have several configuration registers, the set of configuration registers in a very simple chipset might have only one register. The chipset also includes a bus interface
50
for interfacing the chipset to the processor through the main bus
20
.
Some prior art chipsets include scan lines for testing and monitoring the performance of the chipset. The chipset shown in
FIG. 3
includes a diagnostics scan line
52
, which is used for troubleshooting the chipset, and a performance data collection scan line
54
, which is used to collect run-time information for evaluating the performance of the chipset. The scan lines can be realized with any suitable scan techniques such as those disclosed in Fault-Tolerant Computing Theory and Techniques, Vol. 1, Dhiraj K. Pradham, ed., pp. 105-116, 1986.
The scan lines are controlled by scan line logic
56
which is accessible through a separate bus
58
, typically an Inter Integrated Circuit (I
2
C) bus such as I
2
C Version 2.0, published December 1998 by Philips Semiconductors. The scan lines and separate bus allow the chipset to be tested and monitored independently of the processor.
SUMMARY
In a computer system having a processor and a chipset in accordance with the present invention, the chipset is initialized without intervention by the processor.


REFERENCES:
patent: 5918047 (1999-06-01), Leavitt et al.
patent: 6324644 (2001-11-01), Rakavy et al.
Dhiraj, K., et al;Fault-Tolerant Computing Theory and Techniques; vol. 1; Englewood Cliffs, NJ; Prentice Hall (1986); pps. 105-116 and 162-164.

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