Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-01-11
2003-11-04
Le, Thong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230010
Reexamination Certificate
active
06643195
ABSTRACT:
THE FIELD OF THE INVENTION
The invention relates to random access memory for data storage. More specifically, the invention relates to a magnetic random access memory device with self-healing capability.
BACKGROUND OF THE INVENTION
Magnetic Random Access Memory (MRAM) is a non-volatile memory that may be used for long-term data storage. An MRAM device typically includes an array of magnetic memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.
Each magnetic memory cell typically includes a data storage layer and a reference layer. Typically, the logic state of a magnetic memory cell depends on the relative orientations of magnetization in its data storage and reference layers. The magnetization of each memory cell assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent logic values of “0” and “1.”
The data storage layer of a magnetic memory cell is usually a layer or film of magnetic material that stores alterable magnetization states. These alterable magnetization states typically include magnetizations that form in a direction that is parallel to what is commonly referred to as the easy axis of the data storage layer.
The reference layer of a magnetic memory cell is usually a layer of magnetic material in which magnetization is fixed or “pinned” in a particular direction. In a typical prior magnetic memory cell, the reference layer is formed so that its magnetization is pinned in a direction that is parallel to the easy axis of the data storage layer. As a consequence, the orientation of magnetization in the reference layer of a prior magnetic memory cell is typically parallel to the easy axis of the data storage layer.
A magnetic memory cell is typically in a low resistance state if the orientation of magnetization in its data storage layer is parallel to the orientation of magnetization in its reference layer. In contrast, a magnetic memory cell is typically in a high resistance state if the orientation of magnetization in its data storage layer is anti-parallel to the orientation of magnetization in its reference layer.
A prior magnetic memory cell is usually written by applying external magnetic fields that rotate the orientation of magnetization in the data storage layer from one direction to the other along its easy axis. The magnetization orientation of a selected memory cell may be changed by supplying current to a word line and a bit line crossing the selected memory cell. The currents create two orthogonal magnetic fields that, when combined, switch the magnetization orientation of a selected memory cell from parallel to anti-parallel or vice versa. This causes the magnetic memory cell to switch between its high and low resistance states.
The logic state of the magnetic memory cell may be determined during a read operation by measuring its resistance. The resistance state may be sensed by applying a voltage to a selected memory cell and measuring a sense current that flows through the memory cell. Ideally, the resistance is proportional to the sense current.
Hewlett-Packard Company, the assignee of the present invention, is also the assignee of several other patents related to MRAM technology, including: U.S. Pat. No. 6,188,615, entitled MRAM DEVICE INCLUDING DIGITAL SENSE AMPLIFIERS, filed Oct. 29, 1999, and issued Feb. 13, 2001; U.S. Pat. No. 6,163,477, entitled MRAM DEVICE USING MAGNETIC FIELD BIAS TO IMPROVE REPRODUCIBILITY OF MEMORY CELL SWITCHING, filed Aug. 6, 1999, and issued Dec. 19, 2000; U.S. Pat. No. 6,128,239, entitled MRAM DEVICE INCLUDING ANALOG SENSE AMPLIFIERS, filed Oct. 29, 1999, and issued Oct. 3, 2000; U.S. Pat. No. 6,111,783, entitled MRAM DEVICE INCLUDING WRITE CIRCUIT FOR SUPPLYING WORD AND BIT LINE CURRENT HAVING UNEQUAL MAGNITUDES, filed Jun. 16, 1999, and issued Aug. 29, 2000; and U.S. Pat. No. 5,982,660, entitled MAGNETIC MEMORY CELL WITH OFF-AXIS REFERENCE LAYER ORIENTATION FOR IMPROVED RESPONSE, filed Aug. 27, 1998, and issued Nov. 9, 1999. These patents are hereby incorporated by reference herein.
The size of memory systems is constantly increasing with time. As the size of memory systems increases, and memory cell sizes get smaller, the probability of memory bits failing, and the memory system failing, increases. Memory system failures can be the result of both temporary and permanent errors.
In order to prevent memory system failures, different forms of error detection and correction processes have evolved. One commonly used system involves the use of parity bits to detect errors. When data is received, the parity of the data is checked against an expected value. When the data does not match the expected parity value (odd or even), an error is determined to have occurred. Although this method works for determining single bit errors, it does not work well for determining multiple bit errors. Further, the simplest parity systems have no mechanism for correcting data errors.
One commonly used error detection and correction process uses error correction codes (ECC). ECC can be based on CRC (cyclic redundancy checksum or cyclic redundancy code) algorithms. ECC codes can be used to restore the original data if an error occurs that is not too disastrous. With CRC algorithms, when data is received, the complete data sequence (which includes CRC bits appended to the end of the data field) is read by a CRC checker. The complete data sequence should be exactly divisible by a CRC polynomial. If the complete data sequence is not divisible by a CRC polynomial, an error is deemed to have occurred. Other techniques, including the use of a BCH code, or a Reed-Solomon code, can be implemented. These codes provide for the correction of a very small number of errors in a data-set. The trade-off with these codes is that they require a substantial amount of data expansion for the ability to correct a small number of bits.
The parity and ECC techniques discussed above are unable to correct large bursts of “hard” or permanent errors in memories—or in order to protect against such, they require significant data expansion. In order to avoid these large bursts of errors, repairs have typically been done off-line with “fuses” or “anti-fuses”, which permanently change the memory addressing. In this technique, commonly referred to as “sparing,” the bad bits are typically re-mapped to a spare block of bits. The identification of errors and the repairs typically occur in memory manufacturing, and the fuses are not updated “on the fly” during operation of the device by the end customer. With such a technique, the number of spare blocks of memory must be determined at the time of design of the memory device.
In commonly-assigned U.S. patent application No. 09/766,354, filed Jan. 19, 2001, and entitled SELF-HEALING MEMORY, a technique is disclosed for providing a self-healing dynamic random access memory (DRAM) using a “hot spare row” for on-line sparing. On-line self-healing capability has not been provided, however, for a block-oriented memory device like an MRAM.
It would be desirable to provide an MRAM memory with an on-line self-healing capability that is not limited to a predetermined number of spare blocks of memory.
SUMMARY OF THE INVENTION
One form of the present invention provides an MRAM device including an array of memory cells. A plurality of traces cross the memory cells. An address decoder coupled to the plurality of traces decodes an address and selects a corresponding subset of the traces. A sparing circuit coupled to the address decoder receives a logical address and outputs a physical address to the address decoder based on memory cell defect information.
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patent: 6119245 (2000-09-01), Hiratsuka
patent: 612
Eldredge Kenneth J.
Smith Kenneth K.
Hewlett-Packard Development Company LP.
Le Thong
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