Self-corrective memory system and method

Details Self-corrective memory system and method Self-corrective memory system and method

1998-03-12

2000-10-31

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 7, 714 38, G06F 1100

Patent

active

061417688

ABSTRACT:
A computer system is provided which performs a self-test of the memory cells of a memory device prior to loading of a computer program into the memory device, so as to determine the locations of defective memory cells. During loading of the computer program, each instruction step, data block and stack declaration is decoded, and the present invention creates and inserts a jump instruction into the original program code to bypass any defective memory cells without interrupting the intended operation of the instruction steps that are loaded into the memory. The loaded program code is then modified to correct any address-referencing that may be changed due to the insertion of the jump instructions. The present invention can even periodically perform a self-test procedure during the normal operation of the computer system so as to locate new defective memory cells and to modify the program code to bypass these newly-located defective memory cells.

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