Self-correcting, solid-state-mass-memory organized by bits and w

Details Self-correcting, solid-state-mass-memory organized by bits and w Self-correcting, solid-state-mass-memory organized by bits and w

1979-06-22

1982-08-17

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365189, G11C 1140

Patent

active

043453198

ABSTRACT:
A mass memory for use with telecommunication equipment comprises a plurality of memory units associated with respective controllers. Each memory unit includes a command module, dialoguing with the associated controller, and a multiplicity of memory modules for the storage of respective information and redundancy bits of a number of data words, one bit of each word being written in an integrated charge-transfer circuit individually assigned thereto and being continuously recirculated when the memory unit is idle. The command module contains a corrective logic which includes a generator of redundancy bits and intervenes during reading and writing phases. An input/output unit, also forming part of the command module, may comprise a switching circuit including a set of multiplexers which may be selectively operated by instructions from the controller to replace a defective memory module by a spare module whose bit-storing circuits already contain the data of the defective module or can receive them in a reinitialization operation. Instead of a single command module, three such modules synchronized with one another can be used to control the reading and writing through majority logic.

REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 3772658 (1973-11-01), Sarco
patent: 3914748 (1975-10-01), Barton
patent: 4198697 (1980-04-01), Kuo et al.
patent: 4247917 (1981-01-01), Tsang et al.

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