Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Patent
1995-06-07
2000-02-22
Peikari, B. James
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
711170, 710119, 710120, G06F 13368, G06F 1208, G06F 1316
Patent
active
060292245
ABSTRACT:
An apparatus is provided that improves memory storage and access speed by repackaging various types of memories, SRAM, DRAM, and Disk, into a single storage unit. Each unit contains a slice of all the various memories along with programmable logic to control the accessing of the memories. This unit appears to the central processing unit (CPU) of a computer system as an extremely large secondary cache. Independent management of each unit greatly reduces bus traffic to implement any particular address space. By using a plurality of these memory units, an extremely large amount of memory can be accessed by the CPU with the speed of accessing a cache system.
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Asthana Abhaya
Haggan Douglas E.
Tai King Lien
Lucent Technologies - Inc.
Peikari B. James
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