Static information storage and retrieval – Read/write circuit – Testing
Patent
1984-05-18
1986-08-26
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Testing
365233, 365194, 371 21, G11C 700
Patent
active
046086692
ABSTRACT:
An on-chip apparatus for generation of timing signals for a large scale integrated (LSI) chip or semiconductor memory array is disclosed. This apparatus may be used both during the production testing of the memory and during normal functional operation. In the testing environment it allows use of much less expensive peripheral test equipment, while also providing for much greater accuracy in determination of whether or not the memory array meets its timing specification. Use during normal functional operation (subsequent to use in the test environment) provides for a guarantee of defect free operation.
REFERENCES:
patent: 3311890 (1967-03-01), Waaben
patent: 3420991 (1969-01-01), Ling
patent: 3439343 (1969-04-01), Stahle
patent: 3474421 (1969-10-01), Stein
patent: 3633174 (1972-01-01), Griffin
patent: 3751649 (1973-08-01), Hart, Jr.
patent: 3921142 (1975-11-01), Bryant et al.
patent: 3924144 (1975-12-01), Hadamard
patent: 3940601 (1976-02-01), Henry et al.
patent: 3944800 (1976-03-01), Beck et al.
patent: 3961251 (1976-06-01), Hurley et al.
patent: 3961252 (1976-06-01), Eichelberger
patent: 3961254 (1976-06-01), Cavaliere et al.
patent: 4001818 (1977-01-01), Radichel et al.
patent: 4038648 (1977-07-01), Chesley
patent: 4049956 (1977-09-01), Van Veen
patent: 4055754 (1977-10-01), Chesley
patent: 4066880 (1978-01-01), Salley
patent: 4171765 (1979-10-01), Lemone
patent: 4195770 (1980-04-01), Benton et al.
patent: 4227244 (1980-10-01), Thorsrud et al.
patent: 4263669 (1981-04-01), Staiger
patent: 4290137 (1981-09-01), Hilker
patent: 4293950 (1981-10-01), Shimizu et al.
patent: 4298980 (1981-11-01), Hajdu et al.
patent: 4404519 (1983-09-01), Westcott
patent: 4481627 (1984-11-01), Beauchesne et al.
Kelley, "Imbedded Memory Test Methods", IBM Tech. Discl. Bulletin, vol. 21, No. 12, May 1979, pp. 4911-4913.
"A Users Handbook of Semiconductor Memories" by E. R. Hnatek, 1977, John Wiley & Sons, Inc., p. 447.
"Electronic Chip-In-Place Test" by P. Goel and M. T. McMahon, AC, IEE Nineteenth Design Automation Conference Proceedings, Jun. 14-16, 1982, IEEE Catalog No. 82CH1759-0 ACM Order No. 477820, pp. 482-488.
"Logic Card Test Apparatus" by P. B. Shattuck, IBM TDB, vol. 13, No. 3, Aug. 1970, p. 605.
"Integrated Circuit Testing" by P. V. Jordan, IBM TDB, vol. 13, No. 5, Oct. 1970, pp. 1093-1094.
"Pattern Generating System" by E. Legnard et al., IBM TDB, vol. 14, No. 2, Jul. 1971, pp. 482-484.
"Arrangement for Minimized Functional Test of LSI Logic Chips" by F. Tsui, IBM TDB, vol. 15, No. 9, Feb. 1973, pp. 2870-2872.
"Single Clock Shift Register Latch" by T. W. Williams, IBM TDB, vol. 16, No. 6, Nov. 1973, p. 1961.
"Comparative Circuit Tester" by E. B. Carey et al., IBM TDB, vol. 16, No. 10, Mar. 1974, pp. 3151-3152.
"Troubleshooting Large-Scale Integrated Circuit Units" by L. D. Howe et al., IBM TDB, vol. 17, No. 7, Dec. 1974, pp. 1941-1944.
"Testing LSI Memory Arrays Using On-Chip I/O Shift Register Latches" by P. S. Balasubramanian et al., IBM TDB, vol. 17, No. 7, Dec. 1974, pp. 2019-2020.
"Combined Test Scanning and Serial-Deserializing Shift Register" by B. M. Ross et al., IBM TDB, vol. 19, No. 2, Jul. 1976, pp. 480-481.
"Memory Testing" by J. Bappert et al., IBM TDB, vol. 19, No. 5, Oct. 1976, p. 1621.
"Pattern Generator for a Multipart Number Test System" by J. N. Arnold et al., IBM TDB, vol. 19, No. 9, Feb. 1977, pp. 3487-3488.
"Delay Testing and Diagnosis of LSSD Shift Register Strings" by K. E. Dimitri, IBM TDB, vol. 20, No. 1, Jun. 1977, pp.307-312.
"Selective Control of Off-Subassembly Drivers to Test Logic Systems" by F. Hsu et al., IBM TDB, vol. 20, No. 11B, Apr. 1978, pp. 4728-4730.
Klara Walter S.
Kwap Theodore W.
Marcello Victor
Rasmussen Robert A.
DeBruin Wesley
Fears Terrell W.
International Business Machines - Corporation
Miller Guy M.
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