Self-clocking pipeline register

Details Self-clocking pipeline register Self-clocking pipeline register

1995-04-21

1996-07-09

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

327141, H03K 19096

Patent

active

055347967

ABSTRACT:
A control module for controlling a data register, a self-clocking data register controlled by such a module and a pipeline of self-clocked pipeline registers. The localized control module includes a flip-flop for indicating whether the data register being controlled is occupied or vacant. Each module includes state machine logic for generating an enable output to the pipeline register when the flip-flop indicates the register was vacant and a load signal indicating data is available for loading into the register has been received. The localized control may be further modified to provide look-ahead in which an enable output is also generated when a load signal has been received and an unload signal has been received.

REFERENCES:
patent: 5142556 (1992-08-01), Ito
patent: 5373204 (1994-12-01), Muramatsu et al.
patent: 5389838 (1995-02-01), Orengo
patent: 5410550 (1995-04-01), Simmons et al.
patent: 5434520 (1995-07-01), Yetter et al.

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