Self-clocking memory device

Details Self-clocking memory device Self-clocking memory device

2007-06-19

2007-06-19

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C365S191000, C365S193000, C713S400000

Reexamination Certificate

active

10663597

ABSTRACT:
A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

REFERENCES:
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patent: 5918245 (1999-06-01), Yung
patent: 6356990 (2002-03-01), Aoki et al.
patent: 6535045 (2003-03-01), Vangal
patent: 6601121 (2003-07-01), Singh et al.
patent: 6874077 (2005-03-01), Lyon
patent: 2002/0157062 (2002-10-01), Greiner

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