Self-clocked logic circuit and methodology

Details Self-clocked logic circuit and methodology Self-clocked logic circuit and methodology

1997-12-18

2000-05-16

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 46, 326 21, H03K 1900

Patent

active

060642327

ABSTRACT:
A circuit and method for clocking for logic circuits use delay line techniques to time the clock signal. The inputs into a logic circuit are associated with a validity signal, which is delayed by a delay line for at least the propagation delay of the logic circuit. The delayed validity signal is used to latch an output signal produced by the logic circuit in response to the inputs.

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