Self-calibration of a PLL with multiphase clocks

Details Self-calibration of a PLL with multiphase clocks Self-calibration of a PLL with multiphase clocks

2007-11-20

2007-11-20

Kumar, Pankaj (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

10718257

ABSTRACT:
A Phase-Locked Loop with multiphase clocks is provided. The Phase-Locked Loop includes a main loop, a calibration loop, and a Demultiplexer. The main loop includes, coupled in series, a Phase Frequency Detector, a Main Charge Pump, a Main Loop Filter, a Multi-Phase Voltage Controlled Oscillator and a Phase-switching Fractional Divider. The calibration loop includes Y Calibration Loop Filters, with Y being an integer, coupled to the Multi-Phase Voltage Controlled Oscillator, and Control Logic for controlling the Phase-Switching Fractional Divider. The Demultiplexer is coupled between an output of the Main Charge Pump and inputs of the Main Loop Filter and the Y Calibration Loop Filters. A Reference Frequency Signal is coupled to the Phase Frequency Detector, a control signal from the Control Logic is coupled to the Demultiplexer, and a Calibration Signal is coupled to a control input of the Control Logic.

REFERENCES:
patent: 6181213 (2001-01-01), Chang
patent: WO 02/27938 (2002-04-01), None
Chan-Hong Park et al, “A 1.8-Ghz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching”, IEEE Journal of Solid-State Circuits, vol. 36, No. 5, May 2001, pp. 777-783, XP002241677.
S. Khursheed Enam et al., “NMOS IC's for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers”, IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1763-1774, XP000329026.
European Search Report dated May 20, 2003 for European Application No. 02-447227.6.

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