Self-calibrating address transition detection scheme

Details Self-calibrating address transition detection scheme Self-calibrating address transition detection scheme

1996-12-27

1998-09-08

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Differential sensing

365211, 3652335, 36518905, 365227, 365194, G11C 704

Patent

active

058055177

ABSTRACT:
An address transition detector receives one or more address signals. The address transition detector provides a transition detection signal in response to a transition of at least one of the address signals. A pulse generator is coupled to receive the transition detection signal and an environmental input. The pulse generator provides a control signal having a delay based upon an environmental input. The environmental control input may be based upon variables such as temperature, supply voltage, or process skew.

REFERENCES:
patent: 4622476 (1986-11-01), Venkatesh
patent: 4742247 (1988-05-01), Venkatesh
patent: 5418479 (1995-05-01), Sambandan
patent: 5465062 (1995-11-01), Fong
David Hoff et al, IEEE Journal of Solid State Circuits, "A 23-ns 256K EPROM with Double-Layer Metal and Address Transition Detection", vol. 24, No. 5, Oct. 1989, pp. 1250-1258.
1986 IEEE Solid-State Circuits Conference, "Session III Non-Volatile and Application Specific Memories", pp. 40-41.

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