Self-aligning vias for semiconductors

Details Self-aligning vias for semiconductors Self-aligning vias for semiconductors

2000-05-30

2002-06-04

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C438S633000

Reexamination Certificate

active

06400030

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductors and more specifically to semiconductor vias.
BACKGROUND ART
In the process of manufacturing integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called “metalization”, and is performed using a number of different photolithographic and deposition techniques.
In one connection process, which is called a “dual damascene” technique, two channels of conductive materials, are positioned in vertically separated planes perpendicular to each other and interconnected by a vertical “via” at their closest point.
The first channel part of the dual damascene process starts with the placement of a first channel oxide layer over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channels. The damascene step photoresist is stripped and a barrier material is deposited to coat the walls of the first channels to prevent electromigration of subsequently deposited channel material into the oxide layer and the semiconductor. The channel material is then deposited and subjected to a chemical-mechanical polishing process which removes the channel material above the first channel oxide layer and damascenes the channel in the first channels.
The via formation step of the dual damascene process starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
It should be noted here that round via areas, which result in cylindrical vias, have been the standard since the inception of the semiconductor industry. This is because they are easy to form, have previously had the greatest tolerance to misalignment of the channels they connect, and are easy to completely fill with conductive material.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel oxide layer is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer into the pattern of the second channels and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier material is then deposited to coat the vias and the second channels. This is followed by a deposition of the second in the second channels and the vias. A second chemical mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by cylindrical vias.
As the width of the channels has decreased in size due to the size reduction in the semiconductor devices which have given integrated circuits their increasing capabilities, a major drawback with having a cylindrical via has started to appear. It is now apparent that such vias are highly sensitive to misalignment of the channels. If the second channel is not placed in exactly the right position, or aligned, over the round via area, the second damascene etch step will not remove the entire cross-sectional area of the round via area. Thus, misalignment causes the cylindrical volume of the vias to be truncated. This means that there is less current carrying capacity and more resistance in the vias between the first and second channels. And in some cases, the cross-sectional area is so small that the vias can not be filled and voids form preventing any contact between the channels at all. This in turn means a higher defect density and a lower yield of integrated circuits.
Even further, as the size of semiconductors are reduced in order to create more capable integrated circuits, this problem gets much worse because the sizes of the channels decrease as do the sizes of the vias.
Problems with alignment are introduced from such factors as aberrations in the lenses used in the photolithographic processes, inaccuracies in the stepping equipment for reproducing images on the semiconductor wafers, photomask alignment problems, etc.
It has long been known that accurate placement of channels and vias were important so methods for reducing the need for this accuracy have been long sought but its importance for smaller and smaller devices have been under appreciated. Previous solutions to these problems have involved improving the accuracy of alignment.
A solution, which would reduce the need for accurate placement has long been considered, but has eluded those skilled in the art. This is especially true since it has long been known that the problems would become more severe with the reductions in integrated circuit size to sub-micron and deep sub-micron levels.
SUMMARY OF THE INVENTION
The present invention provides self-aligning channels by making the via between the channels in the shape of an elongated cross-section volume such that the via cross-section remains the same when there is a tolerance variation in the positions of the channels relative to each other.
The present invention provides a method of manufacturing semiconductors having a high degree of tolerance to misalignment of the channels.
The present invention further provides a method of manufacturing semiconductors having multiple layers of channels with interconnecting vias, which have a high degree of tolerance to misalignment of the channels.
The present invention still further provides an integrated circuit having elongated cross-section vias, which provide constant size vias despite tolerance variations in the positioning of the channels.
The present invention also provides an integrated circuit which has vias that properly connect the semiconductor devices without failures due to voids.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
PRIOR ART is a plan view of aligned channels with a prior art via;
FIG. 2
PRIOR ART is a cross-section of
FIG. 1
along line
2
—
2
;
FIG. 3
PRIOR ART is a plan view of misaligned channels with a prior art via;
FIG. 4
PRIOR ART is a cross-section of
FIG. 3
along line
4
—
4
;
FIG. 5
is a plan view of aligned channels with a self-aligning via;
FIG. 6
is a cross-section of
FIG. 5
along line
6
—
6
;
FIG. 7
is a plan view of misaligned channels with a self-aligning via;
FIG. 8
is a cross-section of
FIG. 7
along line
8
—
8
;
FIG. 9
is a cross-section of a semiconductor gate with a first channel;
FIG. 10
is a cross-section of
FIG. 9
along line
10
—
10
;
FIG. 11
is
FIG. 9
with a stop nitride layer deposition;
FIG. 12
is a cross-section of
FIG. 11
along line
12
—
12
;
FIG. 13
is
FIG. 11
with a via oxide layer deposition;
FIG. 14
is a cross-section of
FIG. 13
along line
14
—
14
;
FIG. 15
is
FIG. 13
with a via nitride layer deposition;
FIG. 16
is a cross-section of
FIG. 15
along line
16
—
16
;
FIG. 17
is
FIG. 15
after deposition of a via photoresist and photolithographic processing to develop the self-aligning via pattern;
FIG. 18
is a cross-section of
FIG. 17
along line
18
—
18
;
FIG. 19
is
FIG. 17
after a nitride etch to remove th

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