Self-aligning data path converter for multiple clock systems

Details Self-aligning data path converter for multiple clock systems Self-aligning data path converter for multiple clock systems

2007-09-25

2007-09-25

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000, C713S501000, C713S503000, C375S354000, C375S358000, C375S359000, C375S362000, C345S613000, C345S614000, C370S304000, C370S324000, C370S350000, C370S395620

Reexamination Certificate

active

11507677

ABSTRACT:
A system and method for aligning an input signal (24) synchronized to a first clock signal (22) with a second clock signal (26) The invention includes a mechanism (106) for generating a third clock signal (354) and an arrangement (352) for loading the input signal (24) in accordance with the third clock signal (354) and reading out an output signal in accordance with the second clock signal (26). In an illustrative embodiment, the invention is used in a sensor system (350) to align detector input data (24), which is synchronized to a data-capture clock (22), with a signal-processing clock (26). The register (352) acts as a data path transitioning stage between the actual time the input data is sampled and the time a processing system (102) clocks in the sampled data.

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