Self-aligned V-grooves and waveguides

Details Self-aligned V-grooves and waveguides Self-aligned V-grooves and waveguides

1993-05-06

1994-08-30

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156647, 156657, 1566591, 156662, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

053424786

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
This invention relates to a method of forming self-aligned V-grooves and planar waveguides, particularly on a silicon substrate.
2. Related Art
Planar silica waveguides comprise three oxide layers (a buffer layer, a core layer and an overlay) formed on a silicon substrate. Typically, the buffer layer is 6 to 10 .mu.m thick, and can be thermally grown in steam or deposited using plasma enhanced chemical vapour deposition (PECVD). In this case, the core layer is a doped film of higher refractive index such as a 2 .mu.m thick arsenosilicate glass (AsG), or a 3 to 6 .mu.m flame hydrolysis layer (FHD) doped with germanium or phosphorus. The overlay, which is deposited after the core layer has been etched and subjected to a reflow/anneal step to remove surface roughness, is usually a 4 to 10 .mu.m thick PECVD oxide film.
V-grooves are formed in (100) silicon wafers by placing the wafers (suitably masked) in ethylene diamine pyrocatechol and water (EDP) or other anisotropic etchant. The etch rate of silicon is orientation dependent, and the slowest etching crystal planes form the side and end walls of the V-grooves. The groove sizes are controlled by the corresponding mask windows, the accuracy of their alignment with the crystal axes, the erosion rate of the edges of the mask, and the relative etch rates of the crystal planes. Typically, the finished widths of V-grooves can be controlled to within 0.5 to 1 .mu.m, such control being achieved using silicon nitride masks and EDP as the etchant.
A one dimensional array of parallel planar waveguides often needs accurate alignment with a one dimensional array of other optical components (such as parallel optical fibres or another array of parallel planar waveguides). Alignment is usually accomplished by providing both arrays with alignment means constituted by pairs of V-grooves. Several factors affect the accuracy of alignment of V-grooves and planar waveguides. In particular, the V-grooves must be etched towards the end of the processing schedule, because of the difficulty of exposing patterns on grooved wafers. Unfortunately, because V-groove etchants attack silica to varying degrees, the late etching of V-grooves will roughen exposed waveguide cores, which will adversely affect their waveguiding properties. These conflicting factors indicate that V-grooves cannot simply be formed as an adjunct to the known waveguide formation process.


SUMMARY OF THE INVENTION

The present invention provides a method of forming at least one V-groove in alignment with at least one planar waveguide on a silicon substrate, the method comprising the steps of simultaneously forming a respective core for the or each waveguide and a respective window for the or each V-groove, covering the or each core with a protective layer, and forming the or each V-groove through the respective window.
The invention also provides a method of forming a pair of V-grooves in alignment with an array of planar waveguides, the method comprising the steps of simultaneously forming cores for the waveguides and windows for the V-grooves, covering the cores with a protective layer, and forming the V-grooves through the windows, the method being such that the V-grooves are foraged one on each side of the array of waveguides.
Advantageously, the or each waveguide core and the or each window are formed by an etching process. Preferably, the method further comprises the steps of forming a buffer oxide layer on the silicon substrate prior to the step of forming the or each waveguide core and the or each window, and wherein the or each waveguide core is foraged on the buffer oxide layer. Conveniently, the buffer oxide layer is formed in a recess in the silicon substrate, and an overlay oxide layer constitutes the protective layer.
Preferably, the or each V-groove is formed by etching through the respective window, and the or each waveguide core is foraged from a layer of doped oxide.
In a preferred embodiment, the method further comprises the steps of forming a

REFERENCES:
patent: 4973133 (1990-11-01), Matz et al.
patent: 5046809 (1991-09-01), Stein
Patent Abstracts of Japan, vol. 9, No. 13, Jan. 19, 1985, (P-328) (1736).
Applied Physics Letters, vol. 51, No. 26, Dec. 28, 1987, pp. 2189-2191.

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