Self-aligned trench isolation scheme for select transistors in a

Details Self-aligned trench isolation scheme for select transistors in a Self-aligned trench isolation scheme for select transistors in a

1993-02-01

1994-05-17

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

365184, 365185, 365 51, G11C 1140

Patent

active

053134192

ABSTRACT:
The present invention provides a self-aligned trench isolation scheme for the MOS select transistors in an alternate metal virtual ground (AMG) EPROM array architecture. The new isolation scheme allows bit line to bit line spacing to be scaled to 0.6 .mu.m and below without compromising either data retention or memory performance characteristics. A new poly stack self-aligned etch scheme is also provided to scale the word line spacing to 0.6 .mu.m and below and, thus, allow a 64 Mbit EPROM array to be realized.

REFERENCES:
patent: 5099297 (1992-03-01), Hazani
Boaz Eitan, et al.; Alternate Metal Virtual Ground (AMG)-A New Scaling Concept for Very High-Density EPROMS; IEEE 1991; vol. 12, No. 8, Aug. 1991, pp. 450-452.
R. Kazerounian, et al.; Alternate Metal Virtual Ground EPROM Array Implemented in a 0.8 .mu.M Process for Very High Density Applications; IEDM 1991; pp. 311-314.
Graham R. Wolstenholme et al.; A Novel Isolation Scheme for Implementation in Very High Density AMG EPROM and Flash Arrays.

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