Self-aligned tin formation by N.sub.2.sup.+ implantation during

Details Self-aligned tin formation by N.sub.2.sup.+ implantation during Self-aligned tin formation by N.sub.2.sup.+ implantation during

1995-08-28

1997-08-12

Niebling, John

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438655, 438659, 438664, 438902, H01L 2128

Patent

active

056565461

ABSTRACT:
A self-aligned TiN/TiSi.sub.2 formation using N.sub.2.sup.+ implantation during a two-step annealing Ti-salicidation process is provided. The leakage currents of n.sup.+ /p junction diodes fabricated using this technology were measured to investigate the phenomena of Al spiking into Si-substrate. The measured reverse-bias leakage current of diode per unit junction area with Al/TiN/TiSi.sub.2 contact is 1.2 nA/cm.sup.2 at -5 Volts, which is less than all of reported data. Also it can sustain the annealing process for 30 min at 500.degree. C. Thus, TiN formed with this technology process provides an effective barrier layer between TiSi.sub.2 and Al for submicron CMOS technology applications.

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