Self-aligned stack formation

Details Self-aligned stack formation Self-aligned stack formation

1998-06-03

2003-05-13

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S736000, C438S745000, C438S756000

Reexamination Certificate

active

06562724

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit polycide gate structures and fabrication methods.
Background Gate Structures
Patterned multi-layer structures, such as those used for gate structures (“word lines”) for dynamic random access memory (DRAM) devices, can be fabricated using the polycide process. As shown in prior art
FIG. 3
, this process typically consists of blanket deposition of a polysilicon layer
310
on the gate oxide
300
, followed by the formation of a low resistivity layer
320
, typically a metal silicide such as tungsten silicide (WSi2). This layer can be formed either by direct deposition or by metal deposition followed by a reaction anneal. Subsequently, a dielectric layer
330
(typically silicon nitride, or silicon dioxide) is deposited over the metal silicide layer. The multi-layer structures are then patterned, using a photoresist, and etched, typically to form narrow lines.
One difficulty with gate stack etching is that some topography is present, since with many conventional isolation technologies the gate stack will be higher atop field oxides than on the active (moat) areas. Thus, a substantial amount of overetch is required to fully clear the gate stack from the areas to be etched.
In addition, for complicated DRAM transistor gate stacks, conventional etches have lower inter-layer selectivities and lower etch uniformity. These etches will only work on stacks with a thick polysilicon layer and minimal wafer topography where it is possible to stop in the polysilicon layer before exposing and removing the gate oxide. Furthermore, two etch steps need to be performed: one to remove the metal silicide and one to remove the polysilicon. Conventional etches also do not have the profile control required to etch gates with lengths of 0.25 microns and below.
Polycide Structures and Methods
The present application discloses a method to simplify conductive stack fabrication processes by using a hardmask to define a pattern for forming a reaction product, such as a silicide, with the lower conductive layers, and then using the reaction product as a self-aligned mask during a selective etch of the rest of the stack. This method of forming a reverse pattern is particularly advantageous in DRAM applications, to form the gate, but can also be used in other applications, such as to form MOS gates.
Advantages of the disclosed methods include:
avoids etching both the metal silicide and polysilicon layers;
formation of metal silicide by the disclosed process produces a self-aligned mask of the polysilicon layer; and
no photoresist is needed in the etching chamber.


REFERENCES:
patent: 4778563 (1988-10-01), Stone
patent: 4863559 (1989-09-01), Douglas
patent: 5387535 (1995-02-01), Wilmsmeyer
patent: 5576244 (1996-11-01), Hayashi et al.
patent: 5591301 (1997-01-01), Grewal
patent: 5654240 (1997-08-01), Lee et al.

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