Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-02-08
2003-05-27
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S321000, C438S257000, C438S266000
Reexamination Certificate
active
06570213
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a non-volatile semiconductor memory device and, more particularly, to a self-aligned split-gate flash memory cell and its contactless NOR-type memory array for high-density mass storage applications.
2. Description of Related Art
A non-volatile semiconductor memory device is known to store charges in a floating gate by means of either Fowler-Nordheim tunneling or hot-electron injection through a thin tunneling-oxide layer from a semiconductor substrate for programming operation and to remove or erase charges stored in a floating gate by means of Fowler-Nordheim tunneling through a thin tunneling-oxide layer to a semiconductor substrate or to a control gate for erasing operation. Based on the cell structure, the non-volatile semiconductor memory devices of the prior arts can be basically divided into two categories: a stack-gate structure and a split-gate structure.
A typical stack-gate structure of the prior arts is shown in
FIG. 1A
, where a thin tunneling-oxide layer
101
is formed over a semiconductor substrate
100
; a doped polycrystalline-silicon layer
102
being acted as a floating gate is formed over a thin tunneling-oxide layer
101
; an intergate dielectric layer
103
of preferably an oxide-nitride-oxide (ONO) structure is formed over the floating gate
102
; a doped polycrystalline-silicon layer capped with a silicide layer is formed over an intergate dielectric layer
103
to act as a control gate
104
; a source diffusion region is formed with a double-diffused structure having a shallow heavily-doped diffusion region
106
a
formed within a deeper moderately-doped diffusion region
105
a
; a shallow heavily-doped drain diffusion region
106
b
is formed in a semiconductor substrate
100
; a sidewall dielectric spacer
107
is formed over the sidewalls of the stack-gate structure. The stack-gate length of a device can be patterned by using a minimum-feature-size of technology used and this device is recognized to be a one-transistor cell. However, the scaling of a stack-gate device shown in
FIG. 1A
becomes more difficult because a deeper double-diffused source structure is required to have a larger overlapping area between the floating gate and the double-diffused source structure for efficiently erasing stored electrons in a floating gate without producing the band-to-band tunneling effects. Moreover, the punch-through effect becomes a serious concern for programming using channel hot-electron injection as the stack-gate length becomes shorter.
A typical split-gate structure of the prior arts is shown in
FIG. 1B
, where a floating gate
112
is formed over a thin tunneling-oxide layer
111
and can be patterned by using a minimum-feature-size of technology used; a thicker oxide layer
113
is formed over a floating gate
112
and a semiconductor substrate
100
; a control gate
114
is formed over a thicker oxide layer
113
and is then patterned by a critical masking step; the source and drain diffusion regions
115
and
116
are formed through a patterned control-gate
114
and a patterned floating gate
112
as a mask for self-aligned implantation. It is clearly seen that the gate-length of a device is much larger than a minimum-feature-size of technology used and is in general recognized to be a 1.5 transistor cell. Moreover, the alignment tolerance of the critical masking step for defining the control gate becomes a major issue as the split-gate structure is further scaled for high-density mass storage applications.
FIG. 1C
shows another type of the split-gate structure, in which a stack-gate structure consisting of a thin tunneling-oxide layer
121
, a floating gate
122
, an intergate dielectric layer
123
, and a control gate
124
can be patterned by using a minimum-feature-size of technology used; a polycrystalline-silicon spacer
125
is formed over one sidewall of the patterned stack-gate structure having a thicker oxide layer
126
formed on a semiconductor substrate
100
and is acted as a select gate; a heavily-doped source diffusion region
127
a
and a double-diffused drain structure consisting of a shallow heavily-doped drain diffusion region
127
b
within a deeper moderately-doped drain diffusion region
128
are formed. Basically, a non-critical masking step is required to remove a polycrystalline-silicon spacer formed over another sidewall of the patterned stack-gate structure and much better split-gate length controllability can be obtained as compared to a split-gate structure shown in FIG.
1
B. However, the parasitic resistance of the select gate is high, because the select gate is formed by using only a doped polycrystalline-silicon spacer. As a consequence, the operation speed will be limited by a higher RC time constant of the select gate.
SUMMARY OF THE INVENTION
A self-aligned split-gate flash memory cell and its contactless NOR-type memory array for high-density mass storage applications are discolsed by the present invention. The floating-gate width of the present invention is formed by a shallow-trench-isolation (STI) structure having a higher coupling ratio and the embedded double-sides erase cathodes. The floating-gate length of the present invention is defined by a sidewall dielectric spacer formed over a sidewall in the common-source region and, therefore, can be controlled to be much smaller than a minimum-feature-size of technology used. A steep or one-side tapered floating-gate structure is formed and the sidewall of the steep or one-side tapered floating-gate is oxidized to form a field-emission cathode for efficiently erasing stored electrons in the floating-gate to the control gate. The control gate of the present invention is formed by a planarized conductive layer and the control-gate length is defined by another sidewall dielectric spacer formed over the same sidewall. Therefore, the control-gate length of the present invention can be controlled to be smaller than a minimum-feature-size of technology used. The afordmentioned self-aligned split-gate structure is used to implement a contactless NOR-type memory array, in which a plurality of word lines are formed in parallel with the control-gates in a row being connected to form a word line; a plurality of common-source conductive bus lines are sited over the flat beds formed alternately by the common-source diffusion regions and the etched raised field-oxide layers along the common-source lines; a plurality of common-drain conductive islands are formed over the common-drain diffusion regions; and a plurality of bit-lines are formed perpendicularly to the plurality of word lines and are integrated with the plurality of common-drain conductive islands. The common-source conductive bus lines and the common-drain conductive islands are formed by a highly conductive layer and are also acted as the dopant diffusion sources for forming very shallow heavily-doped source/drain diffusion regions. Therefore, the self-aligned split-gate flash memory cell of the present invention not only overcomes the major issues encountered by the split-gate structure of the prior arts but also can offer a smaller cell size for high-density mass storage applications as compared to the stack-gate structure of the prior arts.
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Seiichi Aritome, Advanced Flash Memory Technology and Trends for File Storage Application.
Dry-Etching Various Types of Thin Films, 555-558.
Manufacturing Methods, 641-650.
Nelms David
Silicon Based Technology Corp.
Tran Long
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