Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-12-04
2001-01-30
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S346000, C257S401000, C257S900000, C438S303000, C438S306000
Reexamination Certificate
active
06180988
ABSTRACT:
The present invention relates to a semiconductor device, and, more specifically, to a structure of fabricating a metal oxide semiconductor field effect transistor (MOSFET).
BACKGROUND OF THE INVENTION
With the advent of Ultra Large Scale Integrated (ULSI) technologies, the sizes of semiconductor devices have gotten smaller and smaller than ever, resulting in the packing density of a wafer being continuously increased.
Metal oxide semiconductor field effect transistors (MOSFETs) have been traditionally used and widely applied in semiconductor technologies. As with the trend of the integrated circuits, the fabrication of the MOSFET also meets various issues such as short channel effect. One of the issues is hot carriers that will inject into gate oxide, which is overcome by the development of lightly doped drain (LDD) structure. Parasitic capacitance is a main reason to degrade the speed of the MOSFET, which also causes high power for operating the devices. Typically, the reasons to generate the parasitic capacitance are the gate capacitance, gate-to-drain overlap capacitance, the junction capacitance and the gate fringing capacitance.
The requirement ofthe ULSI CMOS technology is the need for devices operated at low supply voltage and at a high speed. Thus, to minimizing the parasitic capacitance is a key way to achieve high speed and low power devices for CMOS ULSI devices“. See “Impact of Reduction of Gate to Drain Capacitance on Low Voltage Operated CMOS Devices, Kyoji Yamashita et al., 1995, Symposium on VLSI Technology Digest of Technical Papers.”. Prior art approaches to overcome these problems have resulted in the development of the gate-side air-gap (GAS) structure to reduce the parasitic capacitance in the MOSFET. Please see “A Gte-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs38, M. Togo et al., 1996, Symposium on VLSI Technology Digest of Technical Papers. High speed and low power operation devices are achieved by using the GAS structure in MOSFETs. This effectively reduced the gate fringe capacitance of the MOSFETs. However, it is difficult to reduce the valve of fringing field capacitance (C
FR
), due to the difficulty of scaling down the dielectric spacer thickness as scaling down the device dimension. The C
FR
becomes more important as the gate length is reduce to deep sub micron-meter range.
SUMMARY OF THE INVENTION
The method of the present invention includes forming a silicon dioxide layer on the substrate to serve as a gate oxide. A polysilicon layer is then deposited on the silicon dioxide layer. Next, lithography and etching steps are used to form a gate structure. Subsequently, a silicon oxynitride layer is formed on the substrate, and covering the gate structure. Silicon nitride side-wall spacers are formed on the side walls of the gate. An amorphous silicon layer is formed on the substrate, the side-wall spacers, and the top of the polysilicon gate. Then, the active regions (i.e., the source and the drain) are formed by using well-known ion implantation. The amorphous silicon layer acts as a buffer to prevent the substrate from damage during ion implantation.
A wet oxidation is subsequently carried out to convert the amorphous silicon into a doped oxide layer. Simultaneously, the ions in the original amorphous layer will diffuse into the substrate, thereby forming a lightly doped drain (LDD) adjacent to the drain. An etching process is then utilized to etch the oxide layer. Therefore, oxide side-wall spacers are formed on the silicon nitride side-wall spacers. Then, a metal silicide layer is formed on the top of the gate, and on the source and the drain. The silicon nitride side-wall spacers are removed and air gaps are formed between the gate and the side-wall spacers. Then, a low energy pocket ion implantation is performed to dope ions into the substrate via the air gaps. Next, an oxide is formed by chemical vapor deposition on the substrate, spacers and over the gate. Then, a rapid thermal process (RTP) is carried out for annealing.
The MOSFET includes a gate oxide formed on a substrate. A thin dielectric layer is formed on the side walls of the gate. A gate is formed on the gate oxide. A first metal silicide layer is formed on top of the gate to increase the conductivity of the gate. Spacers are formed on the substrate and are separated from the gate by a space. Air gaps are formed between the gate and the spacers. First doped ion regions are formed aligned to the air gaps in the substrate and under a portion of the dielectric layer. Second doped ion regions are formed under the spacers in the substrate and next to the first doped ion regions. Third doped ion regions are formed in the substrate next to the second doped ion regions. The third doped ion regions have relatively highly doped ions to the first doped ion regions. The second doped ion regions is formed with immediately highly doped ions between the first and the third doped ion regions. Preferably, the concentration of the first doped ion regions is about 5E17 to 5E20 atoms/cm
3
. While the concentrations of the second and third doped ion regions are about 1E20 atoms/cm
3
and 1E20 to 5E21 atoms/cm
3
, respectively.
REFERENCES:
patent: 5766969 (1998-06-01), Fulford, Jr. et al.
patent: 5770507 (1998-06-01), Chen et al.
patent: 6051861 (2000-04-01), Togo
Kyoji Yamashita et al.,Impact of the Reduction of the Gate to Drain Capacitance on Low Voltage Operated CMOS Devices,1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 69-70.
M. Togo et al.,A Gate-side Air-gap Structure (GAS) to Reduce the Parasitic Capacitance in MOSFETs,1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39.
Ruth DeJule,Meeting the Ultra-Shallow Junction Challenge,Semiconductor International, Apr. 1997, pp. 50-56.
Eckert II George C.
Harness & Dickey & Pierce P.L.C.
Saadat Mahshid
Texas Instruments--Acer Incorporated
LandOfFree
Self-aligned silicided MOSFETS with a graded S/D junction... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Self-aligned silicided MOSFETS with a graded S/D junction..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self-aligned silicided MOSFETS with a graded S/D junction... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2494318