Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
1999-05-27
2001-05-29
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S413000, C438S166000, C438S592000
Reexamination Certificate
active
06239452
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
This invention relates generally to ultra-large scale integration (ULSI) MOS integrated circuits. More particularly, it relates to a method for fabricating deep submicron CMOS integrated circuits with a self-aligned silicide gate electrode so as to eliminate poly-Si depletion and to suppress the penetration effects of boron ions.
As is generally well-known, a CMOS (complementary metal-oxide semiconductor) device is comprised of an N-channel MOS device and a P-channel MOS device. In particular, deep-submicron CMOS is the primary technology for ULSI (Ultra-Large Scale Integration) systems. In order to increase the speed of the MOS devices, there has existed in the microelectronics industry over the last two decades a continuing trend of scaling-down the structures to smaller and smaller sizes. However, as the device dimensions are scaled down, the gate oxide thickness has to be likewise reduced down to provide optimal device performance.
Thus, there has been proposed heretofore of using a P
+
-type polycrystalline silicon (poly-Si) gate so as to provide a surface channel feature in P-channel MOS devices in deep-submicron CMOS structures. This is due to the fact that surface-channel P-channel MOS devices with P
+
-type poly-Si gates can improve short-channel and sub-threshold I-V characteristics and produce better controllability of the threshold voltage. Typically, BF
2
+
ions are implanted simultaneously with the forming of the P
+
poly-Si gate and a P
+
-N shallow junction. The presence of fluorine ions during the BF
2
implantation enhances the diffusion of boron ions. As a result, there will be a penetration of boron ions through the gate oxide which introduces boron ions to the underlying silicon substrate. Boron penetration results unfortunately in degrading the reliability of the devices, such as positive shifts in the threshold voltage, increased sub-threshold swing, and increased electron trapping.
Accordingly, one of the major concerns for existing dual gate CMOS technology is the problem of boron penetration due to gate oxide scaling-down. Another major concern caused by the gate oxide reduction is poly-Si gate depletion which produces an “excess oxide thickness” that can be quite significant in an ultra-thin gate oxide. The poly-Si depletion will degrade the drive current ability of the P-channel MOS devices. Therefore, the problems of boron penetration and poly-Si gate depletion are considered to be the two important factors which limit the performance of deep submicron devices.
In view of the foregoing, there still exists as need of a method for fabricating deep-submicron CMOS integrated circuits with a self-aligned silicide gate electrode so as to eliminate poly-Si depletion and to suppress the penetration effects of boron ions.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a method for fabricating deep sub-micron CMOS integrated circuits with a self-aligned silicide gate electrode.
It is an object of the present invention to provide a method for fabricating deep submicron CMOS integrated circuits with a self-aligned silicide gate electrode so as to eliminate poly-Si depletion and to suppress the penetration effects of boron ions.
It is another object of the present invention to provide a method for fabricating a self-aligned silicide gate electrode for deep submicron MOS devices utilizing a metal-induced crystallization process.
It is still another object of the present invention to provide a MOS device having a self-aligned silicide gate structure which includes a Nickel silicide layer formed between the gate oxide and the polycrystalline silicon gate electrode.
In accordance with a preferred embodiment of the present invention, there is provided a method for fabricating a deep submicron MOS device having a self-aligned silicide gate structure. A gate oxide is formed on a surface of a semiconductor substrate. An amorphous silicon layer is deposited on a surface of the gate oxide. The amorphous silicon layer is patterned so as to form a gate electrode on a surface of the gate oxide. Shallow source/drain extension regions are formed on opposite sides of the gate electrode and in the semiconductor substrate. Sidewall spacers are formed on sidewalls of the gate electrodes. Highly-doped source/drain regions are then formed on opposite sides of the sidewall spacers and in the semiconductor substrate.
A thin Nickel layer is deposited over the semiconductor substrate. Thereafter, the semiconductor substrate is heated to cause metal-induced crystallization of the amorphous silicon layer into polycrystalline silicon in order to form a Nickel silicide layer between the gate oxide and the polycrystalline silicon gate electrode and Nickel silicide layers over the highly-doped source/drain regions. Finally, an unsilicided Nickel layer is removed from a surface of the sidewall spacers.
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Lin Ming-Ren
Pramanick Shekhar
Xiang Qi
Advanced Micro Devices , Inc.
Booth Richard
Chin Davis
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