Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-14
2001-04-24
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S328000, C257S329000, C257S365000
Reexamination Certificate
active
06222229
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to insulated gate field-effect transistors (IGFETS), and more particularly the invention relates to reducing gate to drain capacitance in IGFETS including lateral and vertical MOSFETS, especially for use with high frequency power MOSFET devices.
Reduction of gate to drain feedback capacitance (C
gd
or C
rss
) in MOSFET devices is desired in order to maximize RF gain and minimize signal distortion. C
gd
is critical since it is effectively multiplied by the voltage gain of the device or C
effective
=C
rss
(1+gmR
1
) where gm is the transconductance and R
1
is the load impedance.
Adler et al., U.S. Pat. No. 5,252,848 discloses an FET structure which includes a performance enhancing conductor shield covering the gate electrode and a portion of the drain region of the FET. A description of such a device operating as a 2 GHz RF transistor is in Technical Digest IEDM conference, 1996, pages 87-90. While the external shield reportedly reduces C
gd
, the dominant component of C
gd
(gate over drain next to channel) is not shielded. Further, while the external shield is applicable to lateral MOS transistors (LDMOS), the external shield cannot be used with vertical transistors. Additionally, process costs in fabricating such devices can be high.
Copending patent application Ser. No. 08/905,513 filed Aug. 4, 1997, now U.S. Pat. No. 14987-42, discloses a field effect transistor including a lateral MOSFET (LDMOS) and a vertical MOSFET (DMOS) transistor which has reduced gate to drain capacitance by providing a buried shield plate underlying the gate and between the gate and drain of the transistor. More particularly, the transistor comprises a semiconductor body having a major surface, a source region of first conductivity type abutting the surface, a drain region of the first conductivity type abutting the surface and spaced from the source region by a channel of a second conductivity type opposite to the first conductivity type, and a gate electrode overlying the channel and part of the drain and insulated therefrom by a dielectric material. The shield plate is formed prior to the gate and is positioned under the gate and between the gate and the drain and is insulated therefrom. The shield plate preferably includes a contact for electrically biasing the shield plate such as by a fixed DC potential and/or an AC ground potential through a capacitive element. While the structure is an improvement over this structure in U.S. Pat. No. 5,252,848, supra, the gate overlapping the shield plate does not reduce input capacitance.
The present invention is directed to a MOSFET structure having effective reduction of gate to drain parasitic capacitance and reduction of input capacitance.
SUMMARY OF THE INVENTION
In accordance with the present invention a high frequency power field effect device having improved reliability is provided with a self-aligned shield structure between the gate and drain of the device. In preferred embodiments there is no overlap of the gate on the shield, and the shield is not located between the gate and source thereby reducing input capacitance.
In fabricating a field effect device in accordance with the invention a layer of gate material is deposited on an oxide layer on a major surface of a semiconductor substrate, the gate material is selectively masked, and then the exposed gate material is etched along with some of the underlying oxide layer thereby forming a raised gate element on the oxide layer. Thereafter a dielectric layer is formed over the gate element and the oxide layer, and a layer of conductive material is then deposited on the dielectric layer. The dielectric material is then selectively removed by anisotropic etching leaving dielectric material only around the gate element as a self-aligned shield. The dielectric material can then be removed by selective masking and etching between the gate and the source leaving the shield adjacent to the gate and overlying the drain.
Advantageously, there is no need for complex or costly processing, and both the gate to drain capacitance and the input capacitance is minimized since gate to shield overlap is minimized and the shield is removed between the source and gate. Further, hot carrier injection and related parameter shifts which adversely affect reliability are reduced. The peak impact ionization rate at the channel to drain junction is reduced, and the location of the peak impact ionization rate is shifted deeper into the semiconductor substrate and away from the gate oxide and drift region surface.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.
REFERENCES:
patent: 5252848 (1993-10-01), Adler et al.
patent: 5359221 (1994-10-01), Miyamoto et al.
patent: 5574294 (1996-11-01), Shepard
patent: 5798278 (1998-08-01), Chan et al.
patent: 5825065 (1998-10-01), Corsi et al.
patent: 5883396 (1999-03-01), Reedy et al.
patent: 5912490 (1999-06-01), Hebert et al.
patent: 5973367 (1999-10-01), Williams
patent: 5977588 (1999-11-01), Patel
patent: 5981998 (1999-11-01), Frisina et al.
patent: 402158171 (1990-06-01), None
patent: 402267971 (1990-11-01), None
patent: 405110102 (1990-11-01), None
patent: 405152342 (1993-06-01), None
U.S. application No. 09/139,532, Sze Him Ng et al. (Art Unit 2815), Aug. 25, 1998.
Hebert Francois
Ng Szehim
Cree Inc.
Lee Eddie C.
Ortiz Edgardo
Townsend and Townsend / and Crew LLP
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