Self-aligned sacrificial oxide for shallow trench isolation

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

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438427, 438435, 438437, 438221, 438296, 148DIG50, H01L 2176

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active

057312419

ABSTRACT:
The present invention provides a method of manufacturing a sacrificial self aligned sub-atmospheric chemical vapor deposition (SACVD) O.sub.3 TEOS layer 50 70 over a trench oxide 40 to protect the trench oxide from excessive subsequent etch steps. The SACVD O.sub.3 TEOS layer has a higher deposition rate over the trench oxide layer 40 than over the surrounding non-trench thermally grown pad oxides. The trench oxide is preferably formed using a process of PECVD, LPTEOS, or O.sub.3 -TEOS. The invention provides two preferred embodiments: (1) a first self aligned sacrificial O.sub.3 TEOS oxide layer 50 deposited before the pad oxide etch and (2) a second self aligned sacrificial O.sub.3 TEOS oxide layer 70 deposited before the sacrificial implant oxide etch. The invention can be applied in a variety of situations where the trench oxide is exposed to damaging etches.

REFERENCES:
patent: 5275965 (1994-01-01), Manning
patent: 5453395 (1995-09-01), Lur
patent: 5498565 (1996-03-01), Gocho et al.
patent: 5536681 (1996-07-01), Jang et al.
patent: 5665635 (1997-09-01), Kwon et al.
"Trench Isolation Technology with Lum Depth n-and p-wells for a Full-CMOS SRAM Cell with a 0.4um nt/pt spacing" by K. Ishimaru et al., 1994 Symposium VLSI Technology Digest of Technical Papers, pp. 97-98 (1994).

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