Self-aligned resistive plugs for forming memory cell with...

Static information storage and retrieval – Systems using particular element – Resistive

Reexamination Certificate

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C365S163000

Reexamination Certificate

active

06545903

ABSTRACT:

FIELD OF INVENTION
The present invention relates generally to semiconductor devices and more particularly to phase change material memory cells and methods for fabricating phase change material memory cells.
BACKGROUND OF THE INVENTION
Phase change materials are alloys in which the structural states of the material may be electrically switched between generally amorphous and generally crystalline local order in a controlled fashion. In these materials, the crystalline state is known to have a lower resistivity than the amorphous state. Such materials are sometimes used to form memory storage devices, for example, where the structural state of the material is indicative of data or other information stored in a particular cell. In some such phase change memory cells, binary data may be stored where the low resistivity crystalline state is used to indicate a binary “0” and the higher resistivity amorphous state indicates a binary “1” or vice versa. The nature of phase change materials also allows controlled setting or “programming” of the material state to one or more intermediate states or local orders between the completely amorphous and completely crystalline states. This characteristic allows use of these materials in other (e.g., non-binary) memories. In this regard, the electrical switching of such materials need not take place between completely amorphous and completely crystalline states. Rather, the electrical switching may be performed in incremental steps so as to provide a “gray scale” represented by a multiplicity of conditions of local order along a range between the completely amorphous and the completely crystalline states.
Another feature of phase change materials is the ability to program memory cells without first having to erase the cell. For instance, in a binary phase change material memory cell, the cell may be programmed directly to either a “1” or to a “0”, regardless of the previous state. In programming memory cells constructed of phase change material, an electrical current of sufficient magnitude is passed through the material, usually in the form of a pulse of limited time duration and controlled magnitude. The programming current causes thermal and/or electrically induced structural changes in the material in order to set the structure to a given state (e.g., completely amorphous, completely crystalline, or an intermediate state). As programming current flows, the phase change material melts into an amorphous state, regardless of the initial state. Where a relatively short duration current pulse is applied, the material cools quickly, and remains in a generally amorphous state. This effectively sets or “programs” the cell material to a electrical high resistivity (e.g., a binary “1”, for example).
Alternatively, where a longer duration pulse is used, the material cools more slowly, and transitions into a generally crystalline state having a relatively low resistivity (e.g., used to indicate a binary “0”). By controlling the pulse duration and the current magnitude, therefore, the memory cell having such phase change material may be programmed or set to either an amorphous or crystalline state in order to function as a binary data store. In this regard, the duration and current amplitude may further be controlled or varied so as to achieve any desired final state (e.g., after cooling), by which non-binary information storage may be achieved. The cell may thereafter be read by applying a current pulse of lower magnitude (e.g., low enough to prevent material melting), by which the resistivity of the cell material (e.g., and hence the value of the data stored or programmed therein) can be ascertained.
A conventional phase change material memory cell
10
is illustrated in
FIGS. 1
a
and
1
b,
having a volume of phase change material
12
of the type described above, which goes through a state change depending upon a current
14
passing therethrough. The cell
10
is connected to a MOSFET type transistor
20
formed in a semiconductor memory device
2
for programming and reading of the cell
10
. The phase change material
12
is situated between an overlying conductive contact
16
and an underlying resistive structure or plug
18
laterally surrounded by a high resistivity material
30
. The plug
18
and the material
30
are formed over another conductive contact
32
, which in turn, is connected to a source/drain structure
22
of the transistor
20
by a conductive via structure
34
. The upper contact
16
is connected to a power supply rail connection
36
(e.g., V
CC
in
FIG. 1
a
) by another via structure
38
, from which programming and/or read current is selectively derived using the transistor
20
.
The transistor
20
further includes a gate
24
and a second source/drain structure
26
connected to a column select line contact C
n
using a via structure
40
. The column line C
n
is selectively used to conduct current from the power supply contact
36
through the cell material
12
, the resistor plug
18
, and the transistor
20
by connection to a power ground using one or more control transistors (not shown), by which the memory cell
10
and the state of the phase change material
12
may be programmed (e.g., written) and/or read. Such operations are performed on the cell
10
when the transistor
20
conducts between the source/drain regions
22
and
26
, according to a signal at the gate
24
. The gate
24
is controlled by row select logic (not shown) in the memory device
2
, by which the cell
10
(e.g., and other cells in a logical row connected to the same row select logic signal) is operated on.
As illustrated in
FIG. 1
b,
when a current
14
, such as a programming current pulse, is applied to the cell
10
, which passes through the resistive plug
18
, heating of the phase change material
12
results near the interface between the material
12
and the plug
18
in a localized region
50
in the volume of material
12
. One problem with the use of a single resistive plug
18
in the design of the memory cell
10
is the localized nature of the area or region
50
affected by the heating of the resistive plug
18
. Although the plug
18
generates some amount of heat, the heating effect is somewhat inefficient because it is only localized to the bottom of the phase change material
12
in region
50
.
It is noted in
FIGS. 1
a
and
1
b,
that the volume of the affected phase change material in the region
50
determines how much resistivity difference results between the programmed and unprogrammed states (e.g., between the amorphous and crystalline states in a binary memory). Thus, it is desirable to impact a greater volume of phase change material by the heating (e.g., in region
50
) to make it easier to differentiate between the binary states (e.g., or between any number of achievable states in a non-binary memory structure). For a given programming current level (e.g., or more generally for a given amount of applied energy), an improvement in the heat delivery over that provided by the single resistive plug
18
would allow a greater volume of phase change material
12
being programmed. Alternatively or in combination, less energy could be applied to achieve the same amount of affected material in the region
50
. Thus, it is seen that a need exists for improving the energy transfer efficiency of phase change material memory cell programming operations.
It is also noted in
FIGS. 1
a
and
1
b
that the structure of the conventional memory cell
10
has a further disadvantage. While a programming current
14
is applied to the cell
10
, the underlying resistive plug
18
acts as a heat source to apply heat to the phase change material in the region
50
. However, at the same time, the upper conductive contact
16
acts as a heat sink, drawing heat energy away from the phase change material
12
. This is because the conductive contact
16
is highly conductive, both electrically and thermally (e.g., the contact
16
is typically fashioned from metal). Thus, in order to extend the affected region
50
upwards (e

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