Self-aligned production method for an insulated gate...

Details Self-aligned production method for an insulated gate... Self-aligned production method for an insulated gate...

2007-05-29

2007-05-29

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S331000, C257S587000, C257SE29120, C257SE29134, C257SE29137, C257SE21621, C257SE21328, C257SE21131, C257SE27152

Reexamination Certificate

active

10537834

ABSTRACT:
The invention relates to a manufacturing method for an insulated gate semiconductor device cell, comprising the steps of forming a cell window (3) in a layered structure that is located on top of a semiconductor substrate (1), forming at least one process mask that partially covers the cell window (3). In forming the cell window (3), at least one strip (41, 42) of the layered structure is left to remain inside the cell window (3) and at least one strip (41, 42) is used to serve as an edge for the at least one process mask (51, 52).The invention further relates to an insulated gate semiconductor device, comprising a semiconductor substrate (1) having an essentially planar top surface and an insulated gate formed on the top surface by a layered structure (2) that comprises at least one electrically insulating layer (22), wherein at least one strip (41, 42) of the layered structure (2) is disposed on a third area of the top surface between an edge of the insulated gate and a first main contact (6).

REFERENCES:
patent: 5234851 (1993-08-01), Korman et al.
patent: 5703383 (1997-12-01), Nakayama
patent: 62-211955 (1987-09-01), None
patent: 62-229977 (1987-10-01), None

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