Self-aligned planar monolithic integrated circuit vertical trans

Details Self-aligned planar monolithic integrated circuit vertical trans Self-aligned planar monolithic integrated circuit vertical trans

1992-03-31

1992-09-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 59, 437162, 148DIG10, 148DIG11, H01L 21265

Patent

active

051513781

ABSTRACT:
A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.

REFERENCES:
patent: 4357622 (1982-11-01), Magdo et al.
patent: 4512815 (1985-04-01), Khadder et al.
patent: 4577397 (1986-03-01), Komatsu et al.
patent: 4719185 (1988-01-01), Goth
patent: 4978630 (1990-12-01), Kim
patent: 4999309 (1991-03-01), Buynoski

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