Self-aligned planar DMOS transistor structure and its...

Details Self-aligned planar DMOS transistor structure and its... Self-aligned planar DMOS transistor structure and its...

2005-11-15

2005-11-15

Dang, Trung (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S329000, C257S335000, C257S341000, C438S268000, C438S299000

Reexamination Certificate

active

06965146

ABSTRACT:
A self-aligned planar DMOS transistor structure is disclosed, in which a p-body diffusion region is selectively formed in an n−
+epitaxial silicon substrate; a self-aligned p+contact diffusion region is formed within the p-body diffusion region through a first self-aligned implantation window surrounded by a first sacrificial dielectric spacer; a self-aligned n+source diffusion ring is formed in a surface portion of the p-body diffusion region through a second self-aligned implantation window formed between a protection dielectric layer and a self-aligned implantation masking layer surrounded by the sacrificial dielectric spacer; a self-aligned source contact window is formed on the self-aligned n+source diffusion ring surrounded by a sidewall dielectric spacer and on the self-aligned p+contact diffusion region surrounded by the self-aligned n+source diffusion ring; and a heavily-doped polycrystalline-silicon gate layer is selectively silicided in a self-aligned manner.

REFERENCES:
patent: 5930630 (1999-07-01), Hshieh et al.
patent: 6121089 (2000-09-01), Zeng et al.
patent: 6277695 (2001-08-01), Williams et al.
patent: 6369425 (2002-04-01), Ferla et al.
patent: 6747312 (2004-06-01), Boden, Jr.

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