Self-aligned NPN transistor with raised extrinsic base

Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – With lattice constant mismatch

Reexamination Certificate

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C257S197000, C257S200000

Reexamination Certificate

active

07026666

ABSTRACT:
A self-aligned bipolar transistor and a method of formation thereof are provided. The bipolar transistor has a raised extrinsic base such that the link base resistance is reduced by providing an extrinsic base which is thicker than the intrinsic base. The increase in thickness of the extrinsic base provides a less resistive layer of the heavily doped base region. The method of forming the bipolar transistor includes depositing a first epitaxial layer on a substrate to form a base region having an intrinsic base region and an extrinsic base region. The extrinsic base region is raised by depositing a second epitaxial layer over a portion of the first epitaxial layer such that the thickness of the extrinsic base layer is x and the thickness of the intrinsic layer is y, wherein x>y. The second epitaxial layer is deposited using a chemical vapor epitaxial device where the concentration of Ge to Si is gradually reduced from above 5% to close to 0% during the epitaxy process. As such, the second epitaxy layer has the highest concentration of Ge near the interface of the first and second epitaxy layer. The concentration of Ge is gradually reduced to near 0% at the top surface of the second epitaxy region.

REFERENCES:
patent: 4157269 (1979-06-01), Ning et al.
patent: 4871684 (1989-10-01), Glang et al.
patent: 4879255 (1989-11-01), Deguchi et al.
patent: 4980738 (1990-12-01), Welch et al.
patent: 5061652 (1991-10-01), Bendernagel et al.
patent: 5117271 (1992-05-01), Comfort et al.
patent: 5159429 (1992-10-01), Bendernagel et al.
patent: 5244821 (1993-09-01), Ham et al.
patent: 5320972 (1994-06-01), Wylie
patent: 5340753 (1994-08-01), Bassous et al.
patent: 5516708 (1996-05-01), Li et al.
patent: 5516710 (1996-05-01), Boyd et al.
patent: 5587327 (1996-12-01), Konig et al.
patent: 5599723 (1997-02-01), Sato
patent: 5773350 (1998-06-01), Herbert et al.
patent: 5804486 (1998-09-01), Zambrano et al.
patent: 5930635 (1999-07-01), Bashir et al.
patent: 6153488 (2000-11-01), Yoshino
patent: 6180442 (2001-01-01), Gris
patent: 6190984 (2001-02-01), Ryum et al.
patent: 6218711 (2001-04-01), Yu
patent: 6287930 (2001-09-01), Park
patent: 6376322 (2002-04-01), Gris
patent: 6492237 (2002-12-01), Kalnitsky et al.
patent: 6617220 (2003-09-01), Dunn et al.
patent: 2002/0132438 (2002-09-01), Dunn et al.
patent: 2003/0057458 (2003-03-01), Freeman et al.
Stanley Wolf Ph.D. and Richard N. Tauber Ph.D. in Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, 1986, pp. 399-400.
Stanley Wolf, et al., Silicon Processing for the VLSI ERA, Lattice Press, Sunset Beach, CA pp. 191-194, 1986.
S.M. SZE, VLSI Technology, pp. 51-129 & 448-461, 1983, McGraw-Hill Book Company.
M. Racanelli, et al., Ultra High Speed SiGe NPN for Advanced BiCMOS Technology, Siliocon RF Platform Technologies, Conexant Systems, Inc. Newport Beach, CA.

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