Self-aligned N+/P+ doped polysilicon plugged contacts to N+/P+ d

Details Self-aligned N+/P+ doped polysilicon plugged contacts to N+/P+ d Self-aligned N+/P+ doped polysilicon plugged contacts to N+/P+ d

1995-11-08

1998-02-17

Powell, William

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

1566361, 1566441, 1566571, 437 41, 437225, 437228, H01L 2100

Patent

active

057188009

ABSTRACT:
A method for preparing an SRAM or DRAM structure on a substrate with an oppositely doped well therein, a field oxide region extending above and between the well and the substrate, first and second NMOS transistors on the silicon substrate, an NMOS word line transistor over the field oxide region, and a PMOS transistor on the silicon well. The source and drain regions of each of the PMOS transistor and the first and second NMOS transistors each have a doped polysilicon plug making contact therewith. The NMOS word line has a polysilicon plug contacting the gate electrode thereof. Each polysilicon plug is isolated one from another, has the same doping as the region with which it makes contact, and is self-aligned to surrounding structures due to etchant selectivities and photoresist masks. The SRAM or DRAM structure is formed in an inventive process having two masking steps, where each masking step opens areas for self-aligned plugs having a common doping and opens a region above the NMOS word line.

REFERENCES:
patent: 5015594 (1991-05-01), Chu et al.
patent: 5022958 (1991-06-01), Favreau et al.
patent: 5112765 (1992-05-01), Cederbaum et al.

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