Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-04-10
2004-02-10
Fahmy, Jr., Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S390000, C257S401000
Reexamination Certificate
active
06690058
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to a flash memory cell and its memory array and, more particularly, to a self-aligned multi-bit flash memory cell and its contactless flash memory array.
DESCRIPTION OF THE RELATED ART
A flash memory cell structure can be basically divided into two categories: a stack-gate structure and a split-gate structure, in which the stage-gate structure having the gate length of a cell defined by a minimum-feature size (F) of technology used is often used in existing high-density flash memory system. The stack-gate flash memory cells can be interconnected to form different circuit configurations based on the basic logic function, such as NOR, NAND and AND. A stack-gate flash memory cell can be programmed by channel hot-electron injection to have different threshold-voltage levels for a multi-bit storage. However, the endurance of the cell and the sensing of the threshold-voltage levels become a difficult task, especially the gate length of a stack-gate flash memory cell is scaled. Therefore, a dual-bit flash memory cell with two floating-gate structures becomes a major trend of developments.
FIG. 1A
shows a cross-sectional view of a dual-bit flash memory cell, in which two stackgate transistors
22
G,
20
G spaced by a select-gate transistor
24
G are formed on a semiconductor substrate
26
; two common N
+
/N
−
diffusion regions
22
A,
20
A are separately formed in each side of the gate region; a select-gate line (SG) is formed above two common N
+
/N
−
diffusion regions and two stack-gate transistors and on a gate dielectric layer
24
A being formed on a semiconductor substrate
26
. Since the stackgate transistor, the select-gate transistor and the common N
+
/N
−
diffusion region can be defined by a masking photoresist step with a minimum-feature F, the cell size of each bit in a dual-bit flash memory cell can be designed to be equal to 4F
2
if the select-gate line and its space can be defined to be a minimum-feature-size F.
FIG. 1B
shows a top plan view of a dual-bit flash memory cell shown in FIG.
1
A. Apparently, the cell size of each bit shown in FIG.
1
A and
FIG. 1B
can be made to be comparable to that of a NAND-type flash memory array due to the contactless structure. However, there are several drawbacks that can be easily observed from FIG.
1
A and FIG.
1
B: very high parasitic capacitance between the select-gate line (SG) and the common N
+
/N
−
diffusion regions
22
A,
20
A; very high parasitic capacitance between the select-gate line (SG) and the control-gate lines
22
C,
20
C; isolation between the common N
+
/N
−
diffusion regions is poor for the regions outside of the select-gate region
24
A; and isolation between nearby select-gate lines is very poor for the regions under the control-gate lines
22
C,
20
C. It should be emphasized that poor isolation between nearby select-gate lines may result in an erroneous data reading from nearby cells under the same control-gate line.
It is therefore an objective of the present invention to provide a self-aligned multi-bit flash memory cell having a cell size of each bit being smaller than 2F
2
.
It is another objective of the present invention to provide a self-aligned multi-bit flash memory cell being programmed by a mid-channel hot-electron injection with much better programming efficiency and much smaller programming power.
It is a further objective of the present invention to provide a highly conductive common-source/drain bus line for each of bit-lines in a contactless multi-bit flash memory array with much smaller bit-line resistance and much smaller bit-line parasitic capacitance with respect to the semiconductor substrate and the word lines.
It is yet another objective of the present invention to provide a highly conductive metal line for each of word lines in a contactless multi-bit flash memory array with much smaller word-line resistance and much smaller word-line parasitic capacitance with respect to the bit-lines.
Other objectives and advantages of the present invention will be more apparent from the following description.
SUMMARY OF THE INVENTION
A self-aligned multi-bit flash memory cell and its contactless multi-bit flash memory array are disclosed by the present invention. The self-aligned multi-bit flash memory cell is formed on a semiconductor substrate of a first conductivity type having an active region isolated by two parallel shallow-trench-isolation (STI) regions and can be divided into three regions: a common-source region, a gate region, and a common-drain region, in which the gate region is located between the common-source region and the common-drain region. The common-source/drain region comprises a first/second sidewall dielectric spacer being formed over each sidewall of the gate region and on a portion of a first/second flat bed being formed by a common-source/drain diffusion region and the etched first/second raised field-oxide layers, a common-source/drain conductive bus line being formed over the first/second flat bed outside of the first/second sidewall dielectric spacer, and a first/second planarized thick-oxide layer being formed over the common-source/drain conductive bus line and the first/second sidewall dielectric spacer. The gate region comprises a first floating-gate structure having a first floating-gate layer (FG
1
) formed on a first gate-dielectric layer and a second floating-gate structure having a second floating-gate layer (FG
2
) formed on a second gate-dielectric layer, wherein the first floating-gate structure and the second floating-gate structure being spaced with a spacing dielectric layer are formed in the active region; and a planarized control-gate layer (CG) over an intergate dielectric layer is at least formed over the first/second floating-gate structure, the spacing dielectric layer, the sidewalls of the first/second sidewall dielectric spacers, and the raised field-oxide layers for the first embodiment of the present invention. A first interconnect-metal layer is formed over the intergate-dielectric layers on the common-source/drain regions and the planarized control-gate layer (CG) to act as a word line, wherein the first interconnect-metal layer together with the planarized control-gate layer are simultaneously patterned by a masking dielectric layer and its two sidewall dielectric spacers. An implanted region of a first conductivity type is formed in a semiconductor substrate under the second floating-gate structure, wherein the implanted region comprises a shallow implant region for threshold-voltage adjustment and a deep implant region for forming a punch-through stop. Similarly, if the intergate dielectric layer for the first embodiment of the present invention is replaced by an intergate-dielectric layer being only formed over the first/second floating-gate layers and the spacing dielectric layer in the active region, the self-aligned multi-bit flash memory cell becomes the second embodiment of the present invention.
A contactless multi-bit flash memory array of the present invention is formed on a semiconductor substrate of a first conductivity type having a plurality of parallel STI regions and a plurality of active regions formed alternately. A plurality of common-source bus-line regions and a plurality of virtual-gate regions are formed alternately and transversely to the plurality of parallel STI regions, wherein each of the plurality of virtual-gate regions comprises a pair of gate regions being located in each side portion and a common-drain bus-line region being located between the pair of gate regions. Each of the plurality of common-source bus-line regions comprises a pair of first sidewall dielectric spacers being formed over each sidewall of nearby virtual-gate regions and on a portion of a first flat bed being alternately formed by a common-source diffusion region of a second conductivity type and an etched first raised field-oxide layer; a common-source conductive bus line being formed over the first flat be
Fahmy Jr. Wael
Pizarro-Crespo Marcos D.
Pro-Techtor Inter-national Services
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