Self-aligned metallization for semiconductor device and process

Details Self-aligned metallization for semiconductor device and process Self-aligned metallization for semiconductor device and process

1987-08-27

1989-04-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437192, 437193, 437194, 437200, 357 59, H01L 21283

Patent

active

048227498

ABSTRACT:
A self-aligned metallization for an MOS device is described in which a first layer of tungsten is selectively deposited on the exposed silicon surfaces of the device including at least the source, drain and gate regions of the device, a layer of material providing nucleation sites for tungsten is selectively formed across insulating oxide regions of the device, and a second tungsten layer is selectively deposited on the nucleating layer and the exposed first tungsten layer to provide interconnection across the oxide regions. In addition to having a low electrical resistivity, such a metallization enables relaxed mask alignment and etching tolerance requirements, and is therefore useful in VLSI circuits.

REFERENCES:
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patent: 4445266 (1981-08-01), Mai et al.
patent: 4589196 (1984-10-01), Anderson
patent: 4630357 (1985-08-01), Rogers et al.
patent: 4643777 (1984-12-01), Maeda
patent: 4660276 (1985-08-01), Hsu
patent: 4751198 (1985-09-01), Anderson
patent: 4764484 (1987-10-01), Mo

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