Self-aligned/maskless reverse etch process using an...

Details Self-aligned/maskless reverse etch process using an... Self-aligned/maskless reverse etch process using an...

2000-11-06

2003-07-15

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S427000, C438S435000

Reexamination Certificate

active

06593210

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to processing a semiconductor substrate. In particular, the present invention relates to a maskless method of forming insulation regions within a substrate.
BACKGROUND ART
In the semiconductor industry, there is a continuing trend toward higher device densities. Fabrication of very large scale integrated circuits (VLSI) and ultra large scale integrated circuits (ULSI) requires that resist materials, lithographic processes, and exposure tools meet necessary performance demands for high throughput manufacturing of sub-micron feature size devices. In particular, the semiconductor industry is producing with increasing frequency integrated circuits having structures which are markedly less than 1 &mgr;m. The increased integration density increases the requirements imposed on the photolithographic process.
Integrated circuits typically contain a plurality of conductive lines, such as bus lines, bit lines, word lines, and logic interconnect lines and a plurality of electrical devices, such as MOSFETS, on a semiconductor substrate. The conductive lines and electric devices are typically separated from each other by insulation regions/materials. The spacing of interconnection lines and electrical devices generally constitutes a limiting factor in terms of integration and various functional characteristics of the integrated circuit. Consequently, reliable and cost effective methods of providing the insulation regions/materials are desired. In this connection, it is common to employ isolation technologies such as using shallow trench isolation, LOCOS (LOCal Oxidation of Silicon), and recessed oxide isolation to form isolation regions.
One conventional method for providing insulation regions/materials, such as trench filling and active site isolation, includes the utilization of a mask or photoresist layer.
FIGS. 1-3
illustrate this conventional method.
Referring to
FIG. 1
, a semiconductor structure
10
is shown with a substrate
12
having a plurality of active regions
20
and a plurality of trenches
14
therein. The trenches
14
therein define the active regions
20
of the substrate
12
. An insulation material
16
is deposited over the substrate
12
. A photoresist
18
is patterned on the semiconductor structure
10
so that the patterned photoresist
18
is positioned over the trenches
14
leaving the portion of the insulation material
16
over the active regions
20
exposed.
Referring to
FIG. 2
, the insulation material
16
exposed (over the active regions
20
) is removed from the semiconductor structure
10
using any suitable technique, such as an anisotropic etching technique. The insulation material
16
is removed down to a level approximately equivalent to the upper surface of the semiconductor substrate
12
.
Referring to
FIG. 3
, the patterned photoresist
18
is removed from the semiconductor structure
10
by use of any suitable method, such as wet chemical etching or plasma ashing, leaving a portion of the insulation material
16
in the trenches
14
. The surface of the semiconductor structure
10
is then planarized by any suitable method, such as using CMP techniques (chemical-mechanical polishing), so that the upper surface of the active regions
20
of the semiconductor substrate
12
and the insulation material
16
formed inside the trenches
14
are substantially co-planar.
While the above-described trench isolation method is commonly employed in the art of advanced integrated circuit fabrication, such a method is not entirely without problems. In particular, there is a concern in ensuring that the photoresist is properly patterned so that the patterned photoresist only and accurately covers the insulation material located within the trenches. Because it is difficult to align the patterned photoresist directly above the trenches, there may be an insufficient amount of photoresist above the trenches to provide trench protection during a subsequent etching process. This can lead to the undesirable removal of the insulation material located within the trenches during a subsequent etching process. In particular, an improperly positioned patterned photoresist may result in the formation of voids within the trenches, and more notably between the insulation material inside the trenches and the active regions.
The desire to build faster and more complex integrated circuits means that the semiconductor industry devotes much effort to reducing the feature sizes of and the separation between conductive features, electrical devices, and active regions on a semiconductor substrate. The risk of void formation increases as semiconductor devices are made increasingly narrower with widths on the submicron level.
The use of a photoresist raises additional concerns, such as the potentially cumbersome steps associated with depositing, using and removing it. In other words, there are numerous potentially cumbersome processing steps associated with depositing the photoresist, irradiating the photoresist, developing the photoresist, stripping the photoresist, and cleaning the semiconductor structure. Any errors or inadequacies associated with any of the photoresist processing steps may potentially render useless the subsequent processing of semiconductor structure.
SUMMARY OF THE INVENTION
The present invention provides an alternative method of forming isolation regions within a substrate. The methods of the present invention do not require the use of photolithography/photoresists to fill the trenches of a substrate with a dielectric material. By eliminating the use of photolithography/photoresists to fill the trenches of a substrate, any concerns and/or problems associated with photolithography and photoresists are thereby eliminated. In particular, alignment of a masking layer over the trenches of a substrate is accurate and reliable when formed in accordance with the present invention.
One aspect of the present invention relates to a method of forming trench isolation regions within a semiconductor substrate, involving the steps of forming trenches in the semiconductor substrate; depositing a semi-conformal dielectric material over the substrate, wherein the semi-conformal dielectric material has valleys positioned over the trenches; forming an inorganic conformal film over the semi-conformal dielectric material; polishing the semiconductor substrate whereby a first portion of the inorganic conformal film is removed thereby exposing a portion of the semi-conformal dielectric material, and a second portion remains over the valleys of the semi-conformal dielectric material; removing the exposed portions of the semi-conformal dielectric material; and planarizing the substrate to provide the semiconductor substrate having trenches with a dielectric material therein.
Another aspect of the present invention relates to a method of forming trench isolation regions within a semiconductor substrate, involving the steps of providing the semiconductor substrate having trenches therein and active regions; depositing a semi-conformal dielectric material over the substrate, wherein the semi-conformal dielectric material has valleys positioned over the trenches and peaks positioned over the active regions; forming an inorganic conformal film over the semi-conformal dielectric material; polishing the semiconductor substrate whereby portions of the inorganic conformal film over the active regions are removed thereby exposing a portion of the semi-conformal dielectric material, and portions of the inorganic conformal film over the valleys of the semi-conformal dielectric material remain; removing the exposed portions of the semi-conformal dielectric material; and planarizing the substrate to provide the semiconductor substrate having trenches with a dielectric material therein.


REFERENCES:
patent: 4576834 (1986-03-01), Sobczak
patent: 4654120 (1987-03-01), Dougherty
patent: 4962064 (1990-10-01), Haskell et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5382541 (1995-01-01), Bajor et al.
patent: 5459096 (1995-10-01), Venk

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