Self-aligned low resistance buried contact process

Details Self-aligned low resistance buried contact process Self-aligned low resistance buried contact process

1996-03-08

2000-06-13

Tsai, Jey

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

438533, H01L 21425

Patent

active

RE0367354

ABSTRACT:
A buried contact is formed in a substrate implantation of phosphorous or arsenic through a window cut into the insulating silicon oxide layer and a superimposed thin silicon layer. The photoresist used to etch the window is cut back a limited amount prior to implantation. The peripheral margin of the buried contact implanted through the exposed part of the thin layer of silicon lowers the threshold voltage of any parasitic MOS device which may be created between the buried contact and the remote N+source or drain structure.

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patent: 4966865 (1990-10-01), Welch et al.
patent: 5064776 (1991-11-01), Roberts
patent: 5147814 (1992-09-01), Takeuchi
patent: 5187122 (1993-02-01), Bonis
patent: 5266523 (1993-11-01), Manning
S. Wolf, Silicon Processing for the VLSI Era--vol. II, pp. 544-545 (Lattice Press 1990).

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