Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-05-08
2003-01-28
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S303000
Reexamination Certificate
active
06511870
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a thin film transistor (TFT). More particularly, the present invention relates to a method of fabricating a polysilicon (poly-Si) TFT with a self-aligned lightly doped drain (LDD), which can form a thinner LDD without adding any photo mask steps.
2. Description of Related Art
Currently in all panel display technologies the liquid crystal display (LCD) technology grows fastest. According the application and the selling of LCD which grows double every year, it plays an important role among display devices. Particularly, the color and the quality of a thin film transistor (TFT) are sufficient to be a competitor of cathode-ray tube.
Today different technological processes of fabricating the TFT are developed. A conventional TFT process includes depositing each layer in turn on a glass substrate. Please refer to
FIGS. 1A-1E
showing schematic, cross-sectional views of a conventional TFT process. The steps of fabricating a conventional TFT process are as followed.
(a) A glass substrate
10
is provided. A pre-treatment is performed on the glass substrate
10
. The pre-treatment includes subsequently depositing a buffer layer and an active layer (not shown), and performing an annealing process on the active layer. The material of the active layer is &agr;-Si. A polysilicon region is defined by photolithography and etching.
(b) A gate insulating layer
20
and a metal layer
25
are subsequently deposited on the glass substrate performed by the pre-treatment.
(c) A gate is defined with a photo resist layer by photolithography and etching.
(c) A gate is defined with a photo resist layer by photolithography and etching.
(d) A light ion doping (N
−
) step is performed with serving the gate as a mask to form a lightly doped region
15
a
in the polysilicon region
15
. The dopant can be phosphorus ions or arsenous ions.
(e) A photo resist
40
is defined by a photo process.
(f) A heavy ion doping (N
+
) step is performed with serving the gate as a mask to form a heavily doped region
15
b
in the polysilicon region
15
. The dopant can be phosphorus ions or arsenous ions.
Thus a thin film transistor (TTT) with the heavily doped region
15
b
and the lightly doped region
15
a
is formed.
However, it needs two steps of forming a photo mask to form the foresaid conventional TFT process. This causes difficulties in processing, misaligned issue, and an increase of resistance. The increasing resistance leads to poor conductivity of a source line, further influencing the reliability and the performance of products of the TFT. Therefore, it is a need to improve the fabricating method for the TFT.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a method of fabricating a polysilicon (poly-Si) TFT with a self-aligned lightly doped drain (LDD), which can form a thinner LDD without adding any photo mask steps. The processes are thus simplified.
Another object of the present invention is to provide a method of fabricating a polysilicon (poly-Si) TFT with a self-aligned lightly doped drain (LDD), which uses a step of oxidizing a metal gate to form a heavily doped region and a lightly doped region. Thus misalignment can be avoided and the process of forming the lightly doped region becomes more precise.
Another object of the present invention is to provide a method of fabricating a polysilicon (poly-Si) TFT with a self-aligned lightly doped drain (LDD), which can simultaneously activate the heavily doped region and is also suitable for a low temperature polysilicon process.
According to the fabricating method of the present invention, at first a polysilicon-island region and a gate insulating layer are subsequently formed on a glass substrate performed by a pre-treatment. Then a metal layer and a cap layer are subsequently formed on the gate insulating layer. The cap layer and the metal layer are defined to form a gate. A heavily doped region is formed in the polysilicon island region with serving the gate as a mask. An activation step is performed on the heavily doped region and a sidewall of the metal layer. The cap layer above the metal layer and the sidewall of the metal layer performed by the activation step are removed. A lightly doped region is formed in the polysilicon-island region with serving the remaining metal layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5476802 (1995-12-01), Yamazaki et al.
patent: 5620905 (1997-04-01), Konuma et al.
patent: 5994192 (1999-11-01), Chen
Chang Jiun-Jye
Chen Chih-Chiang
Chuang Ching-Sang
Elms Richard
Luhrs Michael K.
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