Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
1999-12-14
2002-03-26
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S230000, C438S574000, C438S579000
Reexamination Certificate
active
06362033
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to integrated circuits and more particularly to methods for forming lightly doped source and drain regions (LDD) for MOS transistors.
Lightly doped source and drain regions (LDD) have proved advantageous for MOS transistors in highly integrated circuits. One technique for forming lightly doped drains is as follows. Referring to
FIG. 1A
, a silicon substrate
10
is provided on which field oxide regions
12
are formed. Field oxide regions
12
define an active area in which a transistor
14
is formed. Note that shallow trench isolation may be used in place of field oxide regions
12
. Transistor
14
includes a gate stack
16
and source and drain regions
18
. Gate stack
16
includes a gate dielectric (gate oxide
20
) formed over a gate channel region
22
, a gate doped polycrystalline silicon layer
24
and an insulation cap
26
. Source and drain regions
18
are formed by using gate stack
16
and field oxide regions
12
as a mask and implanting an appropriate dopant by a low energy ion beam to form shallow and lightly doped source and drain regions
18
. The regions may have a depth of 500-700 Angstrom and a dose of approximately 10
13
-10
14
cm
−2
implanted at an ion acceleration voltage of 10 KeV and 10-15 KeV for BF
2
, for example.
Because they are lightly doped, lightly doped source and drain regions
18
do not form satisfactory ohmic contacts with metal or doped poly-crystalline silicon interconnect layers, not shown. To provide for such an ohmic contact, highly doped regions are formed in source and drain regions
18
of transistor
14
, and the interconnect layers connect to those highly doped regions. Hence, referring to
FIG. 1B
, after forming source and drain regions
18
, dielectric spacers
28
are formed by a conventional process on all sides of gate stack
16
thereby insulating gate conductor
24
. The entire structure is then subjected to a second ion implantation process using a high dose, high energy ion beam to form the highly doped regions
30
and, in addition, doped regions
31
under the sidewall spacers
16
, as indicated. After annealing highly doped region
30
to activate the implanted dopants, the width of the channel region under the gate is reduced to the width indicated by L
effective
. Note that L
effective
is typically narrower than the width of the gate because of out-diffusion of dopant in regions
31
into portions
32
of the channel region, such out-diffusion being indicated by the dotted line in FIG.
1
B.
Referring to
FIG. 1C
, highly doped regions
30
are then used for forming interconnect layer contacts to the source and drain regions
18
, such as metal, or doped polycrystalline silicon, contact
32
formed by any conventional process. At the point of contact of metal layer
32
with highly dope region
30
, a silicide layer may be formed to improve contact between metal contact
32
and highly doped region
30
. As is obvious, this process requires two ion implantation procedures to form lightly doped source or drain regions having satisfactory ohmic contacts.
SUMMARY OF THE INVENTION
In one general aspect, the invention features a method for forming a transistor. A gate electrode of a transistor is formed over a substrate. The gate electrode defines a gate channel portion of the substrate. A mask is also formed over the substrate, a portion of the mask extending over a first portion of the substrate adjacent to the gate channel portion of the substrate. The mask defines a second portion of the substrate adjacent to the first portion of the substrate. An ion beam is directed toward the substrate to form a drain or a source region of the transistor adjacent to the gate channel portion of the substrate, the source or drain region including the first and second portions of the substrate. The ion beam implants the second portion of the substrate with a first implantation characteristic. The ion beam passes through the extended portion of the mask to reach the first portion to implant the first portion with a second implantation characteristic, such second implantation characteristic being different from the first implantation characteristic.
In another general aspect, the invention features a method for forming a transistor. A gate stack is formed where the gate stack includes a gate oxide layer, a gate conductive layer, and a gate insulation layer. The gate stack is subjected to an etch to laterally remove portions of the gate conductive layer to undercut a portion of the insulating layer. The etched conductive layer forms a gate conductor defining a gate channel portion of the substrate. The undercut portion of the insulating layer extends beyond the gate conductor to provide an overhang over a first portion of the substrate adjacent to the gate channel portion of the substrate. An ion beam is directed toward the substrate to form a source or drain region of the transistor adjacent to the gate channel portion of the substrate. The source or drain region includes the first portion of the substrate and a second potion of the substrate adjacent to the first portion of the substrate. The ion beam implants the second portion with a first implantation characteristic. The ion beam also passes through the undercut portion of the insulating layer to reach the first portion to implant the first portion with a second implantation characteristic, such second implantation characteristic being different from the first implantation characteristic.
Hence, these aspects of the invention allow for forming an implanted region having two different implantation characteristics during a single implantation step.
Preferred embodiments of the invention may include one or more of the following features.
The first and second implantation characteristics can be first and second dosage concentrations, respectively, where the first dosage concentration is greater than the second dosage concentration. The extended portion of the mask changes characteristics of the ion beam passing therethrough to reduce the dosage concentration implanted by the ion beam in the first portion of the substrate to the second dosage concentration. The extended portion of the mask reduces the current of the ion beam.
The first and second implantation characteristics can also be first and second implantation depths, respectively, where the first implantation depth is greater than the second implantation depth. The extended portion of the mask changes characteristics of the ion beam passing therethrough to reduce the implantation depth of dopants implanted in the first portion of the substrate to the second implantation depth. The extended portion of the mask reduces the voltage of the ion beam so that the penetrating depth of the ion beam passed through the over-hang region is reduced.
The extended portion of the mask can also change other characteristics of the ion beam passing therethrough, such as the angle of incidence of the ion beam with the substrate.
The gate stack is formed by forming a gate oxide layer on a surface of the substrate; forming a conductive layer over the gate oxide layer; depositing an insulating layer over the conductive layer, the insulating layer being selected to change characteristic of an ion beam passing through the insulating layer; and patterning the conductive layer and the insulating layer into a gate stack extending vertically with respect to the substrate.
The mask defines an opening over the second portion. The insulating layer is deposited by depositing the insulating layer with a thickness selected to change characteristics of the ion beam passing therethrough such that the ion implantation in the first portion of the substrate has the second implantation characteristic. The conductive layer is a poly-crystalline silicon layer, typically a polysilicon etch selective to silicon oxide or silicon nitride. The etch is an isotropic etch such as a chemical downstream etch (CDE) using an HBr based plasma or a wet etch using an HNO
3
and HF solution.
Unless otherwise defi
Lee Heon
Park Young-Jin
Elms Richard
Pyonin Adam J.
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