Self-aligned isolation double-gate FET

Details Self-aligned isolation double-gate FET Self-aligned isolation double-gate FET

2005-09-20

2005-09-20

Lee, Eddie (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

C257S365000, C257S288000, C257S412000, C257S388000, C257S347000, C438S157000, C438S283000, C438S279000, C438S299000

Reexamination Certificate

active

06946696

ABSTRACT:
A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

REFERENCES:
patent: 5140391 (1992-08-01), Hayashi et al.
patent: 5188973 (1993-02-01), Omura et al.
patent: 5349228 (1994-09-01), Neudeck et al.
patent: 5733331 (1998-03-01), Peredo
patent: 6492212 (2002-12-01), Ieong et al.
patent: 6580132 (2003-06-01), Chan et al.

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