Self aligned gate

Details Self aligned gate Self aligned gate

2001-05-25

2003-01-14

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S581000, C438S583000, C438S655000, C438S664000, C438S683000, C438S299000, C438S315000

Reexamination Certificate

active

06506670

ABSTRACT:

FIELD
The invention relates generally to the field of integrated circuit fabrication and, in particular, to improved methods for fabricating self aligned transistor gates.
BACKGROUND
The size of integrated circuits continues to decrease while their operation continues to increase in speed and complexity. As the size of integrated circuits decreases, new challenges arise for improved fabrication techniques that provide smaller, more functional circuits without increasing the manufacturing complexity or cost. For example, in a conventional integrated circuit fabrication process for forming a gate structure, the gate is patterned using a photoresist mask to define the gate features. The photoresist mask should be thick enough to protect the gate material, so that the gate material is not completely consumed during the etching process. With ever shrinking integrated circuit geometries, however, the photolithography process tends to require that the photoresist be applied in ever thinner layers, which thinner layers offer less resistance to the etchant, and may thus break down during the etching process and expose the gate material to the etchant.
In the alternative, a hard mask consisting of a relatively thin layer of a material, such as an oxide or a nitride that etches more slowly than the gate material and the photoresist, is used to protect the gate material during the etching process. However, if the top surface of the gate is to be bonded to or further reacted at a later point in time, such as to form a silicide, then the top surface of the gate should be free of any hard mask material that would tend to prevent the silicide from forming. Accordingly, additional steps are typically required to remove the hard mask prior to forming a silicided gate. These additional steps, however, may negatively impact other portions of the overall gate structure, such as a drain spacer or drain liner. Thus, there continues to be a need for techniques which provide improved integrated circuits without significantly increasing manufacturing costs.
SUMMARY
The above and other needs are met by a method for making a gate in an integrated circuit. A gate layer is formed on a substrate, and a blocking layer is formed on the gate layer. The blocking layer is masked with a photoresist layer, and the photoresist layer is developed to define an exposed gate area. The blocking layer is etched in the gate area to expose the gate layer in the gate area, and the photoresist layer is removed. A metal layer is formed on the blocking layer and on the gate layer in the gate area. The metal layer is selectively reacted with the gate layer in the gate area to form a hard mask over the gate layer in the gate area. The metal layer is removed from the blocking layer. The blocking layer is selectively etched without substantially etching the hard mask in the gate area, to expose the gate layer surrounding the gate area. The exposed gate layer is etched to define a gate in the gate area. The hard mask remains on the gate, and functions as an electrical contact to the gate.
Thus the invention provides a means for etching the gate layer to define a gate by using a hard mask to protect the gate during the etch instead of using photoresist. In addition, the hard mask is preferably a reacted metal layer that remains on the gate as an electrical contact, and thus does not need to be removed in an additional later step in the process. Therefore, the invention reduces the complexity and steps necessary to remove a hard mask material when forming a gate.
In various preferred embodiments of the invention, an anti-reflective layer is formed on the blocking layer prior to masking the blocking layer with the photoresist layer. The gate layer preferably comprises polysilicon, and the metal layer preferably comprises at least one of titanium, tungsten, nickel and cobalt, and most preferably cobalt. Thus, the hard mask is preferably a silicide, and most preferably cobalt silicide. The substrate is preferably a gate dielectric layer on top of a semiconducting substrate, which is most preferably silicon.
In a most preferred embodiment, the step of masking the blocking layer with a photoresist layer comprises masking the blocking layer with a negative photoresist layer, and exposing the negative photoresist layer using a positive photoresist mask. The positive photoresist mask is one such as typically is used to expose a positive photoresist layer prior to a gate etch process. Thus, a new mask does not need to be made in order to accomplish the processing described herein.


REFERENCES:
patent: 5907436 (1999-05-01), Perry et al.
patent: 6156632 (2000-12-01), Schuegraf

Affiliated with

Also associated with

Rating

Self aligned gate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Self aligned gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Self aligned gate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3026337