Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-26
2003-09-30
Pham, Long (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000, C257S314000
Reexamination Certificate
active
06627942
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a self-aligned method of forming a semiconductor memory array of floating gate memory cells, and more particularly to an improved method of forming the isolation regions between active regions in which the memory cells are formed.
BACKGROUND OF THE INVENTION
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate, as well as the isolation regions between the active regions that contain these components. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, the present invention uses the technique of self-alignment to achieve the manufacturing of the isolation regions used in a semiconductor memory array, such as one with a floating gate memory cell type.
Figures
FIGS. 1A-1B
show the well known shallow trench process (STI) for forming isolation regions between active regions of a memory array semiconductor device. As shown in
FIG. 1A
, a first layer of insulation material
12
, such as silicon dioxide (“oxide”), is formed on the substrate
10
. A layer of polysilicon
14
(used to form the floating gate) is deposited on top of the layer of insulation material
12
. A silicon nitride layer
16
(“nitride”) is deposited over the polysilicon layer
14
. A suitable photo-resistant material
18
is then applied on the silicon nitride layer
16
and a masking step is performed to selectively remove the photo-resistant material from certain regions (stripes
20
). Where the photo-resist material
18
is removed, the silicon nitride
16
, the polysilicon
14
and the underlying insulation material
12
are etched away in parallel stripes
20
using standard etching techniques (i.e. anisotropic etch process). The etching continues to form trenches
22
that extend down into the substrate
10
. As the silicon substrate is etched to form trench
24
, a slight lateral undercut
26
is formed, where the oxide layer
12
and poly layer
14
overhang the trench
22
. Where the photo resist
18
is not removed, the silicon nitride
16
, the first polysilicon region
14
and the underlying insulation region
12
are maintained.
The structure is further processed to remove the remaining photo resist
18
, which is followed by the formation of an isolation material
24
, such as silicon dioxide, in the trenches
22
(e.g. by depositing an oxide layer, followed by a CMP etch). Then, the nitride layer
18
is selectively removed. The resulting structure is shown in FIG.
1
B. The remaining polysilicon layer
14
and the underlying first insulation material
12
form the active regions in which the memory cells are formed. Thus, at this point, the substrate
10
has alternating stripes of active regions and isolation regions with the isolation regions being formed of the shallow trench insulation material
24
.
The structure in
FIG. 1B
represents a self aligned structure, which is more compact than a structure formed by a non self-aligned method. However, problems can occur with this structure after the isolation is completed and during the formation of the memory cells.
FIG. 1C
illustrates the structure after back processing steps are performed to complete the formation of the memory cell array structure. Poly layer loss is typical in such back processing steps, whereby the side edges of poly layer
14
that at one time extended over to overhang the isolation trench
22
are later are pulled back away from the isolation trench
22
. This results in a gap
6
between the side edges of the poly layer
14
and the edges of the isolation trench
22
, leaving a portion of oxide layer
12
and the substrate
10
exposed and unprotected by the poly layer
14
. Several adverse consequences arise from this condition. First, this structure is prone to silicon pitting in the active region, where processing steps which rely on the protection by poly layer
14
tend to damage oxide layer
12
and substrate
10
in the gap region &dgr;. Further, the electrical performance of the final product is adversely affected because the poly layer
14
(which forms the floating gate that controls conduction in the underlying substrate) no longer overlays the full width of the substrate
10
between adjacent isolation trenches. One further disadvantage of conventional STI isolation is that poly layer lifting occurs (i.e. smiling effect), which means the thickness of the oxide layer
12
near the side edges of the poly layer
14
increases. Poly layer lifting occurs because the poly layer
14
is formed before isolation trench oxide
24
is formed.
There is a need for an isolation process that addresses these problems.
SUMMARY OF THE INVENTION
The present invention solves the aforementioned problems by utilizing a process that self aligns the poly layer to the diffusion edge, where an increased overlap is formed between the side edges of the poly layer and the isolation regions. The process of the present invention can be independently optimized in a self-aligned manner.
The present invention is a self-aligned method of forming isolation and active regions in a semiconductor device, and includes the steps of forming a layer of first material on a semiconductor substrate, forming a plurality of spaced apart trenches that extend through the layer of first material and into the substrate, forming a first layer of insulating material along sidewall portions of the trenches, filling the trenches with an insulating material, removing the layer of first material to expose portions of the substrate, forming a second layer of insulating material on the exposed portions of the substrate, and forming a layer of conductive material on the second layer of insulating material.
In another aspect of the present invention, a semiconductor structure for use in the manufacture of an electrically programmable and erasable memory device includes a substrate of semiconductor material of a first conductivity type, a first layer of insulating material formed on the substrate, a layer of conductive material formed on the first layer of insulating material, a plurality of spaced apart trenches formed through the first layer of insulating material and the layer of conductive material and into the substrate, a second layer of insulation material formed on sidewall portions of the trenches, and a block of insulation material formed in the trenches. For each of the trenches, an edge portion of the layer of conductive material extends over and overlaps with the first layer of insulating material by a predetermined distance A.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
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pate
Gray Cary Ware & Friedenrich LLP
Pham Long
Silicon Storage Technology, Inc
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